An Introduction to Asynchronous Logic and ECS

Asynchronous logic is a widely studied discipline that removes the global clock from traditional synchronous designs. The Global Clock in normal chip design makes sure that all parts of the chip operate at the same speed and at the same time, and is very convenient from the perspective of design. However, these clock rates are very high now - a well-known commercial example is the Intel PentiumPro, which can operate at up to 200MHz. A less well-known example is the newest Alpha chip (the 21164) from DEC, which can operate at up to 500MHz. The generation, distribution and design of this clock and the network which distributes it over a very large chip (approaching 2cm by 2cm), is becoming increasingly difficult. In addition, the power dissipated by these chips is increasing rapdily - up to 50W, the power dissipated by a goodly-sized light-bulb!

Asynchronous logic design attempts to solve these problems by removing the Global Clock signal and replacing it with lots of local signals. This solves quite neatly the clocking problem, and has lots of nice connotations in terms of power dissipation, correctness and the way that we can check that the chip operates correctly before making it.

However, most asynchronous approaches suffer from poor performance . They can be much slower than synchronous designs, and consume up to twice the area of their synchronous counterparts. The ECS project attempts to redress this problem by using engineered design techniques to produce fast systems - the traditional approach generates circuits and systems from specifications written in a higher, more abstract form (similar to the language you might use to write programs at home). This has resulted in significant performance wins for this approach - ECS delivers a reduction of over 60% in local signalling overhead compared to some other approaches.

ECS is still in it's infancy, however, and we are still working hard to make it a viable, valuable, and perhaps most importantly usable approach for designing fast asynchronous circuits and systems.

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Last modified: Fri Oct 11 12:03:20 1996