Asynchronous logic design attempts to solve these problems by removing the Global Clock signal and replacing it with lots of local signals. This solves quite neatly the clocking problem, and has lots of nice connotations in terms of power dissipation, correctness and the way that we can check that the chip operates correctly before making it.
However, most asynchronous approaches suffer from poor performance . They can be much slower than synchronous designs, and consume up to twice the area of their synchronous counterparts. The ECS project attempts to redress this problem by using engineered design techniques to produce fast systems - the traditional approach generates circuits and systems from specifications written in a higher, more abstract form (similar to the language you might use to write programs at home). This has resulted in significant performance wins for this approach - ECS delivers a reduction of over 60% in local signalling overhead compared to some other approaches.
ECS is still in it's infancy, however, and we are still working hard to make it a viable, valuable, and perhaps most importantly usable approach for designing fast asynchronous circuits and systems.