ECS Published Papers

Also note that they're all in a4 paper format - you'll have to use some postscript utility, like psnup or pstops, to get them in usletter format.

People seeing the ECS light!


Access to available internal reports and other documents is granted on a limited basis.

The abstracts of internal reports and other strange and wierd documents can be viewed here .


You can read about the FOCA approach here.

Published ECS Papers On-Line

A 100MIPS Event Controlled ALU

This paper describes the design of an eight bit, event controlled ALU for use in an asynchronous microprocessor. A highly efficient pipelining structure has also been developed, and important aspects of the design methodology employed in the construction of these, and other event controlled systems, is presented.

Let me see it!


An Event Controlled Asynchronous Microprocessor

Sorry, we can't locate postscript source for this paper.

The Design & Simulation of an Event Controlled Asynchronous Microprocessor using VHDL

Can't locate postscript for this paper.

An Event-Controlled Reconfigurable Multi-chip FFT

This paper describes the design of a FFT chip, up to eight of which may be cascaded together to produce continuous streams of transforms of up to 65536 points. The control structure is asynchronous, and hence a fast, very low power, skew-free environment is provided. Aspects of the event controlled methodology used for this, and other designs, is also presented.

Let me see it!


ECSTAC : A Fast Asynchronous Microprocessor

This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given.

Let me see it!


Cache Design for an Asynchronous VLSI RISC microprocessor

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Asychronous Pipelining Techniques and Applications


The Design of a Fast Asynchronous Microprocessor

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High Performance Two-Phase Asynchronous Pipelines

Well, we've gotten a lot of comments telling us that two-phase will never be as good as four-phase asynchronism. Most people see the Journal of VLSI Systems (IEEE) article by Day and Woods as the final word. Recently, we submitted an article for submission to a special IEICE journal issue on asynchronous techniques, which debunked a lot of those comments. We finally got the message and compared the two approaches. The results speak for themselves.

This is the final version of our paper. It will appear sometime in the first half of 1997 in the IEICE ED Journal.

Here it is!


Two-Phase Asynchronous Pipeline Control

We described our methodology better, and backed it up with solid performance figures for static and dynamic logic pipelines. We also briefly describe ECSTAC, our prototype microprocessor currently under testing.

This paper is to be published in the proceedings of Async'97, Eindhoven, Netherlands.

Grab me that!



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Comments and requests can be sent to sam@eleceng.adelaide.edu.au