ECS Internal Report Abstracts

The following is a list of Internal Reports relating to the ECS project. Note that although most have abstracts available, not all of them are accessible as yet. If you're absolutely desperate for one of these internal reports, please contact sam@eleceng.adelaide.edu.au
Access to available internal reports and other documents is granted on a limited basis.

Internal Reports

Abstracts

The full text of these internal reports is only available on request. Unfortunately some of these internal reports are unsuitable for wider release as yet and do not appear on-line on these pages.

Pipelining Principles

 This paper considers a new pipelining technique in asynchronous logic, called the Morton Pipeline . This pipeline has the potential to significantly speed up computation speed when the latency between input data and input event is relatively high.

Event Control of the ALU

Computational Cells of the ALU (version 1)

Computational Cells of the ALU (version 2)

Event Controlled Systems - Techniques and Concepts

This paper shows a number of techniques which can be applied at the architectural and VLSI levels to simplify and/or enhance the ECS design process. It also serves to illustrate the simplicity and power of working in the temporal domain.

An ECS SRAM Design

This paper considers the application of the ECS methodology to the design of a self-timed SRAM system. This system is to be fabricated along with another SRAM system, employing a different control paradagim, for testing.

Design of a Controller for an Event Controlled Cache System

This paper describes the design of a controller for a unified cache in a simple microprocessor. From initial specifications of the cache and the processor interface, a complete control algorithm is developed and simplified, and then used to generate an ECS control circuit.

A Reconfigurable ECS Multi-Module FFT

This paper describes the design of a FFT chip, up to eight of which may be cascaded together to produce continous streams of transforms up to 65536 points. The control structure is asynchronous, and hence a fast, very low power, skew-free environment is provided. Aspects of the event controlled methodology used for this, and other designs, is also presented.

The Design of a QR42 Interface using the ECS Methodology

This paper describes in part the design of a control interface between a four-cycle world and a two-cycle world. The interface is designed using the Event Controlled Systems (ECS) methodology developed at the University of Adelaide. Two distinct approaches to the problem are presented.

Event Controlled Systems Design Methodology using a Temporal Specification Approach (version 2)

This paper details the Event Controlled Systems (ECS) methodology in detail. Control lines are transformed to a new domain - the temporal domain -- while data signals remain untransformed. This transformation makes the representation of two-cycle asynchronous systems simple, and also allows a number of properties of these systems to be checked. Although this is a critical paper which deals with the central issues of Event Controlled Systems, it is not available on-line. Two other papers which deal extensively with the concepts introduced in the paper are Event Controlled Systems (ECS) Design Methodology and Associated Pipelining Techniques and Two-Phase Asynchronous Architectures> .

The ECS Family of Gates

This paper details the range of gates that deal with control and data signals in ECS. All the allowable control-path gates are dealt with in this paper.

Temporal Transition Graphs for Event Controlled Systems

This paper extends the work on Signal Transition Graphs (STGs) to the Event Controlled Systems (ECS) methodology. This allows a number of properties of an ECS circuit to be checked directly as part of the Temporal Transition Graph (TTG) specification.

Event-Controlled Counters

This paper details a number of alternatives for the design of counters using the Event Controlled Systems (ECS) methodology.

Petri Nets applied to the ECS Methodology

In this paper, a modelling tool applicable to ECS circuits, namely Petri Nets, is extended to model accurately the operation of ECS circuits. This allows a number of results pertaining to error checking in the ECS circuit to be gained.

Implementation of an ECS SRAM

This paper presents the design for a SRAM using a delay-model approach. This is the companion paper to report HPCA-ECS-93-6, An ECS SRAM Design .

ECS Compilation Techniques

Pipelined ECS Cache Design

ECS Compilation Techniques (part 2)

A Comparison of Language Features suitable for use in formal temporal specifications

This report compares the features of a number of languages and their available implementations as candidates for use as the basis for a language for Temporal Specification of circuits. A Pascal-like subset of Ada is recommended.

Instruction Set Architecture of ECSTAC-P (version 2.2)

This paper details the instruction set architecture of the prototype microprocessor, ECSTAC-P . It outlines the modes and functions of each instruction and provides the opcodes for each. Instructions are of variable length, ranging from one to four bytes in length.

Instruction Decode & Operand Fetch Process for ECSTAC-P (version 2.2

This paper details the instruction decode and operand fetch stage of the prototype Event Controlled Systems Temporally-specified Asynchronous CPU, ECSTAC-P . The derivation of this is obviously greatly dependent on the instruction coding, and the reader is referred to the Instruction Set Architecture of ECSTAC-P for details.

ECSTACBus : External Bus Protocol for the ECSTAC-P microprocessor

The ECSTAC-P processor is a prototype asynchronous microprocessor with a considerable requirement for high bandwidth communications with memory devices. The method of connection between the memory system and the CPU, namely the memory bus, is detailed in this paper.

Register Control, Tags, and Write Back Strategies for ECSTAC-P

This paper follows on from Instruction Decode & Operand Fetch Process for ECSTAC-P, in which control signals to be sent to both the register unit and the tags unit were devised along with the order in which these signals are to be applied. Further, the signals required in the following stages of the microprocessor pipeline were also determined therein.

This report now details the structure of the register unit and in particular the configuration of the register tags. It also explains two strategies which may be employed in the writing back to registers phase of the microprocessor given that write back always occurs from either the Cache unit or the ALU unit. One strategy always maintains the ordering of instructions, whilst the other only maintains order when necessary.

24 bit Adder, Comparator, and Stack Access Stages for ECSTAC-P

This paper describes the architecture of the two stages which follow the Instruction Decode and Operand Fetch stage of ECSTAC-P. Enclosed in the first stage is a comparator unit and the first of two adder stages, and in the second is the control for stack pointer accessing and the last of the two adder stages.

Interface to Execution Units, the ALU, and the PC structures for ECSTAC-P

This document outlines the simplistic structure of the interface between the final stage of the ACS and the succeeding execution units, these being the ALU and the Cache (BI operations do not require an execution unit as they proceed directly to the PC). The structure of the ALU is also described herein together with the configuration of the Program Counter with particular reference to the interface between this and the outputs from the Cache unit and those pertaining to Branch Instructions.

Instruction and Data Caches for the ECSTAC-P processor

This paper considers the design of Instruction and Data Caches for a prototype asynchronous microprocessor, ECSTAC-P, using the Event-Controlled Systems methodology (ECS). The design is discussed, from the integration aspects in the processor pipeline and simulation issues, right down to the detailed circuits and VLSI design of the systems. A detailed exposition of the control design for both caches is also given. This paper will be available on-line soon.

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