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INSPEC 5218787 B9605-5240D-017
Doc Type: Conference Paper
Title: Efficient 3-D series impedance extraction using effective
internal impedance
Authors: Beom-Taek Lee; Tuncer, E.; Neikirk, D.P.
Affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX,
USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 220-2
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Theoretical/Mathematical
Abstract: The effective internal impedance approach, combined with
the current-filament technique, has been shown to be a very efficient
way to extract frequency dependent resistance and inductance of
uniform interconnects. In this study, we show that this approach can
be extended to find the series impedance of three dimensional
structures. A microstrip bend is studied as a simple example.
(10 Refs.)
Classification: B5240D (Waveguide and cavity theory)
Thesaurus: Electric impedance; Microstrip discontinuities; Waveguide
discontinuities
Free Terms: 3D series impedance; Effective internal impedance;
Current-filament technique; Frequency dependent resistance;
Inductance; Interconnects; Three dimensional structures; Microstrip
bend
Item Availability: CD-ROM.
INSPEC 5218785 B9605-0170J-044
Doc Type: Conference Paper
Title: Two optimizations to accelerated method-of-moments
algorithms for signal integrity analysis of complicated
3-D packages
Authors: Kamon, M.; Krauter, B.; Phillips, J.; Pileggi, L.; White,
J.
Affiliation: Res. Lab. of Electron., MIT, Cambridge, MA, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 213-16
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Theoretical/Mathematical
Abstract: In this paper we present two optimizations to accelerated
Method-of-Moments algorithms. The first is an improved preconditioner
for multipole-accelerated inductance extraction and the second is a
set of several optimizations of the FFT-based convolution used in
precorrected-FFT methods. (8 Refs.)
Classification: B0170J (Product packaging); B0260 (Optimisation
techniques); B0290Z (Other numerical methods)
Thesaurus: Convolution; Fast Fourier transforms; Inductance; Method of
moments; Optimisation; Packaging
Free Terms: Optimization; Accelerated method-of-moments algorithms;
Signal integrity; 3D packages; Preconditioner; Multipole method;
Convolution; Precorrected FFT method; Inductance
Item Availability: CD-ROM.
INSPEC 5218777 B9605-1350H-013
Doc Type: Conference Paper
Title: Low cost, highly integrated MMW MMIC transceiver packages
Authors: Gawrouski, M.; Seashore, C.; Bosch, D.; Lamberg, J.;
Loughran, S.; Rabel, J.
Affiliation: Div. of Defense Syst., Alliant Techsyst., Hopkins, MN,
USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 183
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Practical; Experimental
Abstract: Summary form only given, as follows. A producible, high
density Ka-Band (35 GHz) monolithic transceiver package has been
developed containing a full set of MMIC transmit/receive chips. This
paper presents the results of extensive 3-D electromagnetic high
frequency chip-to-chip and chip-to-microstrip line/packaging
interconnect analyses. The MMIC module includes a novel
chip-on-carrier design with a low cost 'Duroid' soft substrate
performing the RF circuit interconnection with IF amplification.
(0 Refs.)
Classification: B1350H (Microwave integrated circuits); B2570
(Semiconductor integrated circuits); B0170J (Product packaging)
Thesaurus: Integrated circuit design; Integrated circuit
interconnections; Integrated circuit packaging; Microstrip lines;
MIMIC; Transceivers
Free Terms: MMW MMIC transceiver; IC packages; Ka-Band;
Transmit/receive chips; Chip-to-chip/packaging interconnect;
Chip-to-microstrip line/packaging interconnect; Chip-on-carrier
design; Duroid; Soft substrate; RF circuit interconnection; IF
amplification; 35 GHz
Numerical Index: Frequency 3.5E+10 Hz
Item Availability: CD-ROM.
INSPEC 5218776 B9605-0170J-039
Doc Type: Conference Paper
Title: Solderless interconnects for 3D microwave packaging
Authors: Wooldridge, J.
Affiliation: Hughes Aircraft Co., Los Angeles, CA, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 181-2
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Application; Practical; Experimental
Abstract: The electrical performance parameters of solderless
interconnects and the associated package development are reviewed for
a 3D X-band transmit/receive module. The microwave performance over
7-18 GHz, as well as the environmental performance, are discussed
with both theoretical and actual measurements. (0 Refs.)
Classification: B0170J (Product packaging); B1350H (Microwave
integrated circuits)
Thesaurus: Integrated circuit interconnections; Integrated circuit
packaging; Microwave integrated circuits; Modules
Free Terms: Solderless interconnects; 3D microwave packaging;
Electrical performance parameters; Package development; X-band;
Transmit/receive module; Microwave performance; Environmental
performance; 7 To 18 GHz
Numerical Index: Frequency 7.0E+09 to 1.8E+10 Hz
Item Availability: CD-ROM.
INSPEC 5218761 B9605-7310N-005
Doc Type: Conference Paper
Title: A coplanar waveguide probe with applications to thin film
dielectric measurements
Authors: Seltmann, E.W.; Laskar, J.; Smith, K.; Gleason, R.
Affiliation: Sch. of Electron. Comput. Eng., Georgia Inst. of
Technol., Atlanta, GA, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 126-9
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Practical; Experimental
Abstract: A novel approach to thin film dielectric measurements at
microwave and millimeter wave frequencies is investigated using a
coplanar waveguide (CPW) probe. Using the spectral-domain technique,
an admittance model describing the CPW thin film interface system is
determined for reflection measurement techniques, and delay
measurement analysis is performed for thru measurement techniques. To
validate the model, an error analysis is performed with 3D
electromagnetic simulators and CPW S-parameter data from materials
with known dielectric properties. (9 Refs.)
Classification: B7310N (Microwave measurement techniques); B2810
(Dielectric materials and properties); B7310K (Dielectric variables
measurement); B1320 (Waveguide components)
Thesaurus: Coplanar waveguides; Delays; Dielectric measurement;
Dielectric thin films; Microwave measurement; Millimetre wave
measurement; Probes; S-parameters; Spectral-domain analysis
Free Terms: Coplanar waveguide probe; Thin film dielectric
measurements; Millimeter wave frequencies; Microwave frequencies;
Spectral-domain technique; Admittance model; Reflection measurement
techniques; Delay measurement analysis; Error analysis; 3D
electromagnetic simulators; S-parameter data
Item Availability: CD-ROM.
INSPEC 5218752 B9605-0170J-030
Doc Type: Conference Paper
Title: 255 CBGA electrical performance comparison through
package electrical characterization and system
simulations
Authors: Osorio, R.; Casto, J.
Affiliation: Motorola Inc., Chandler, AZ, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 95-7
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Theoretical/Mathematical; Experimental
Abstract: The electrical performance of 255 CBGA packages from
three suppliers are compared. This is done through the extraction of
signal, power, and ground parasitic parameters such as resistance
(R), self-inductance (L), mutual-inductance (M), and capacitance (C),
and through SPICE system simulations. The results indicate that,
although the three CBGAs` electrical performances were different,
they all performed satisfactorily at 100 MHz bus-frequency, for a 2.0
ns through 0.5 ns rise/fall time. A similar behavior in electrical
performance was observed at other frequencies. (0 Refs.)
Classification: B0170J (Product packaging)
Thesaurus: Capacitance; Circuit analysis computing; Circuit noise;
Electric resistance; Inductance; Packaging; SPICE
Free Terms: 255 CBGA packages; Electrical performance comparison;
Electrical characterization; Bus-frequency; Parasitic parameters;
Resistance; Self-inductance; Mutual-inductance; Capacitance; SPICE
system simulations; Rise time; Fall time; 3D electromagnetic
simulation; Transmitted noise; Power bounce; Ground bounce; Ceramic
ball grid array; 100 MHz; 0.5 To 2 ns
Numerical Index: Frequency 1.0E+08 Hz; Time 5.0E-10 to 2.0E-09 s
Item Availability: CD-ROM.
INSPEC 5218751 B9605-6320-010
Doc Type: Conference Paper
Title: Test of 3D stacked microwave TR modules
Authors: Hauhe, M.S.
Affiliation: Hughes Aircraft Co., Los Angeles, CA, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 93-4
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Practical; Experimental
Abstract: The performance of a three dimensional Transmit/Receive
Module for a flat panel active array radar is reviewed. Solderless
interconnects for both front and back side probing of the 3D Module
are discussed as well as test results describing the performance of
the module. (0 Refs.)
Classification: B6320 (Radar equipment, systems and applications);
B5270D (Antenna arrays); B0170J (Product packaging)
Thesaurus: Active antenna arrays; Antenna testing; Heat sinks; Modules;
Radar antennas; Transceivers
Free Terms: 3D stacked microwave TR modules; Transmit/receive module;
Flat panel active array radar; Solderless interconnects; Back side
probing; Front side probing; Test results
Item Availability: CD-ROM.
INSPEC 5218747 B9605-5210-024
Doc Type: Conference Paper
Title: LC: an integrated methodology to model and visualize the
complex electrodynamics of 3D structures
Authors: Gravrok, R.; Piket-May, M.; Thomas, K.
Affiliation: Cray Res. Inc., Chippewa Falls, WI, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 73-6
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Theoretical/Mathematical
Abstract: Equivalent-circuit models are obtained from direct
interpretations of electromagnetic field data. Improved intuitive
understanding is achieved with direct visualization of wave
propagation through 3D structures. Applications to MCMs and
power-distribution networks are described. (0 Refs.)
Classification: B5210 (Electromagnetic wave propagation); B1130
(General circuit analysis and synthesis methods)
Thesaurus: Electromagnetic wave propagation; Equivalent circuits
Free Terms: LC; Electrodynamics; 3D structures; Equivalent-circuit
model; Electromagnetic field; Visualization; Wave propagation; MCMs;
Power-distribution networks
Item Availability: CD-ROM.
INSPEC 5218744 B9605-0170J-028
Doc Type: Conference Paper
Title: Design method of a metallic enclosure considering EMI
using a 3D-FEM
Authors: Tanabe, S.; Nagano, N.; Itoh, T.; Murato, Y.; Mizukawa,
S.; Sato, K.
Affiliation: Mater. & Electron. Devices Lab., Mitsubishi Electr.
Corp., Hyogo, Japan
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 64-6
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Practical; Theoretical/Mathematical
Abstract: The leakage of electromagnetic radiation from a metallic
enclosure with apertures is numerically analyzed by solving Maxwell`s
equations directly using a three dimensional finite element method
(3D-FEM). This method applied for designing a metallic enclosure for
an asynchronous transfer mode digital service unit (ATM-DSU) to
decrease EMI in the range of 30 MHz to 1 GHz. (1 Refs.)
Classification: B0170J (Product packaging); B5230 (Electromagnetic
compatibility and interference); B0290T (Finite element analysis)
Thesaurus: Electromagnetic interference; Finite element analysis;
Maxwell equations; Packaging
Free Terms: Metallic enclosure; EMI; 3D-FEM; Electromagnetic radiation
leakage; Apertures; Maxwell`s equations; Asynchronous transfer mode
digital service unit; ATM-DSU; 30 MHz to 1 GHz
Numerical Index: Frequency 3.0E+07 to 1.0E+09 Hz
Item Availability: CD-ROM.
INSPEC 5218737 B9605-2210B-005 C9605-7410D-094
Doc Type: Conference Paper
Title: Computation of switching noise in PCBs for digital
packages
Authors: Jong-Gwan Yook; Chandramouli, V.; Katehi, L.P.; Sakallah,
K.A.
Affiliation: Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann
Arbor, MI, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.95TH8137)
p. 37-9
Publisher: IEEE
New York, NY, USA
Date: 1995 viii+240 pp.
Country of Publication: USA
ISBN: 0 7803 3034 X
CCC: 0 7803 3034 X/95/$4.00
Language: English
Conf. Date: 2-4 Oct. 1995
Conf. Loc: Portland, OR, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE
Components, Packaging & Manuf. Technol. Soc
Treatment: Practical; Theoretical/Mathematical
Abstract: Simultaneous switching noise in printed circuit boards
for digital packages is computed using a hybrid technique which
combines electromagnetic analysis (3D FEM) and circuit simulation
(HSPICE) for fast and efficient time and frequency domain analysis.
(6 Refs.)
Classification: B2210B (Printed circuit layout and design); B1130B
(Computer-aided circuit analysis and design); B0170J (Product
packaging); B0290T (Finite element analysis); C7410D (Electronic
engineering computing); C4185 (Finite element analysis)
Thesaurus: Circuit analysis computing; Circuit noise; Finite element
analysis; Frequency-domain analysis; Packaging; Printed circuit
design; SPICE; Time-domain analysis
Free Terms: Switching noise; PCBs; Digital packages; Printed circuit
boards; Electromagnetic analysis; 3D FEM; Circuit simulation; HSPICE;
Frequency domain analysis; Time domain analysis
Item Availability: CD-ROM.
INSPEC 5211954 B9604-1265B-087 C9604-5210B-035
Doc Type: Conference Paper
Title: Testability controlled physical design of vertically
stacked integrated circuits
Authors: Reber, M.; Kirsch, A.
Affiliation: Inst. for Electron., Kaiserslautern Univ., Germany
Conf. Title: Proceedings Eighth Annual IEEE International ASIC
Conference and Exhibit (Cat. No.95TH8087)
p. 249-52
Editors: Cook, W.A.; Hull, R.A.; Traver, C.
Publisher: IEEE
New York, NY, USA
Date: 1995 xv+422 pp.
Country of Publication: USA
ISBN: 0 7803 2707 1
CCC: 0 7803 2707 1/95/$4.00
Language: English
Conf. Date: 18-22 Sept. 1995
Conf. Loc: Austin, TX, USA
Treatment: Practical
Abstract: Vertical integration technology is expected to provide
several advantages, such as high packaging density, parallel
processing, high speed operation and an improved reliability. Basic
design aspects for vertically stacked integrated circuits are
discussed in this paper. A novel partitioning method for vertically
stacked integrated circuits (VIC) will be proposed which generates
testable circuit partitions. Generated circuit layouts of partitioned
MCNC benchmark circuits demonstrate the superiority of 3-D circuit
layouts over planar circuit layouts especially for increased circuit
sizes. (6 Refs.)
Classification: B1265B (Logic circuits); B2570 (Semiconductor
integrated circuits); B0170J (Product packaging); B0170N
(Reliability); B1130B (Computer-aided circuit analysis and design);
C5210B (Computer-aided logic design); C7410D (Electronic engineering
computing)
Thesaurus: Application specific integrated circuits; Circuit layout
CAD; Circuit optimisation; Design for testability; Integrated circuit
design; Integrated circuit interconnections; Integrated circuit
packaging; Integrated circuit reliability; Logic CAD; Logic
partitioning
Free Terms: Testability controlled physical design; Vertically stacked
integrated circuits; Packaging density; Parallel processing; High
speed operation; Reliability; Design aspects; Partitioning method;
Testable circuit partitions; Circuit layouts; MCNC benchmark
circuits; 3D circuit layouts; Circuit sizes
Item Availability: CD-ROM.
INSPEC 5202215 B9604-7230G-018 C9604-3240K-004
Doc Type: Journal Paper
Title: Airborne ultrasonic imaging system for parallelepipedic
object localization
Authors: Ossant, F.; Poisson, G.; Tran-Huu-Hue, L.P.; Roncin, A.;
Lethiecq, M.
Affiliation: Fac. de Medecine, GIP Ultrasons, Tours, France
Journal: IEEE Transactions on Instrumentation and Measurement
Vol: 45 Iss: 1 p. 107-11
Publisher: IEEE
Date: Feb. 1996
Country of Publication: USA
ISSN: 0018-9456 CODEN: IEIMAO
CCC: 0018-9456/96/$05.00
Language: English
Treatment: Application; Practical
Abstract: An ultrasonic image device was designed for use in
robotic applications where parallelepipedic objects need to be
manipulated. It is based on ranging measurement by an array of ten
identical airborne ultrasonic transducers with an operating frequency
of 200 kHz and a detection cone angle of approximately 7 degrees. An
electronic scanning associated with a mechanical displacement of the
array covers an area of 0.4*0.4 m in less than 0.5 seconds (100
measurement points). The system was tested in an automatic packaging
line. It allowed a real-time localization of cubic objects as small
as 2 cm and the determination of an emplacement in which a new object
can be put by a robot arm. (7 Refs.)
Classification: B7230G (Image sensors); B7810C (Sonic and ultrasonic
transducers); C3240K (Image sensors); C3390 (Robotics)
Thesaurus: Industrial robots; Ultrasonic imaging; Ultrasonic transducer
arrays
Free Terms: Airborne ultrasonic imaging; Parallelepipedic object
localization; Robotic applications; Ranging measurement; Cross
coupling; Airborne ultrasonic transducers; Detection cone angle;
Electronic scanning; Mechanical displacement; Measurement points;
Automatic packaging line; Real-time localization; Cubic objects;
Robot arm; 3D perception; 200 KHz; 0.4 M; 2 Cm
Numerical Index: Frequency 2.0E+05 Hz; Distance 4.0E-01 m; Size 2.0E-02
m
Item Availability: CD-ROM.
INSPEC 5163460 C9603-5490-002
Doc Type: Journal Paper
Title: Heat-transfer engineering in systems integration: outlook
for closer coupling of thermal and electrical designs of
computers
Authors: Nakayama, W.
Affiliation: Dept. of Mech. & Intelligent Syst. Eng., Tokyo Inst. of
Technol., Japan
Journal: IEEE Transactions on Components, Packaging, and
Manufacturing Technology, Part A
Vol: 18 Iss: 4 p. 818-26
Publisher: IEEE
Date: Dec. 1995
Country of Publication: USA
ISSN: 1070-9886 CODEN: IMTAEZ
CCC: 1070-9886/95/$04.00
Language: English
Treatment: Practical
Abstract: This paper begins with a review of the author`s personal
experience in the research field of computer cooling. It highlights
the need to develop foresight on the possible course of hardware
development in order to provide the package designer with appropriate
heat-transfer data in a timely manner. A question is then raised
about the immediate future of the (indirect) water-cooling
technology. Water-cooling has so far proven effective in cooling
high-end computers which use ECL devices in two-dimensional
packaging. The drive toward higher raw speeds of ECL devices,
however, is going to lose steam-emerging instead is the endeavor to
upgrade system performance by massively-parallel computing which
requires wiring-intensive hardware. Three-dimensional packaging will
meet the demand for short global wiring in systems, but will become a
commercial reality only after the establishment of methodologies for
its design and assembling. One of the key issues in the design of 3-D
computers is the optimum allocation of physical space for electrical
wiring and heat-transfer paths. Intimate coupling of wiring and heat
transfer designs pose challenges to heat-transfer researchers that
have not surfaced in other industrial applications. Items of primary
importance include: the methodology to predict how and temperature
distributions in a field having a wide spectrum of length scales, the
local heat-transfer coefficients in the maze of microscale coolant
channels, the possibly large effect of extraneous factors such as
irregular geometric features of coolant channels and conjugate mode
of heat transfer, and temperature control during assembling of 3-D
structures. (34 Refs.)
Classification: C5490 (Other aspects of analogue and digital computers)
Thesaurus: Computers; Cooling; Design engineering; Packaging; Systems
engineering
Free Terms: Heat-transfer engineering; Systems integration; Thermal
design; Electrical design; Computer cooling; Water-cooling; ECL
devices; Massively-parallel computing; Three-dimensional packaging;
Electrical wiring; Two-dimensional packaging; Temperature
distribution; Temperature control
Item Availability: CD-ROM.
INSPEC 5158269 B9602-2250-007
Doc Type: Journal Paper
Title: Utilizing a low cost 3D packaging technology for consumer
applications
Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, L.
Affiliation: Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
Journal: IEEE Transactions on Consumer Electronics
Vol: 41 Iss: 4 p. 1095-102
Publisher: IEEE
Date: Nov. 1995
Country of Publication: USA
ISSN: 0098-3063 CODEN: ITCEDA
CCC: 0098-3063/95/$04.00
Language: English
Treatment: Application; New development; Practical
Abstract: This paper demonstrates how a low cost three-dimensional
packaging (multichip module-vertical) technology can be utilized to
implement systems for consumer applications. In any application where
system cost, volume and mass are important, this packaging technique
can be advantageous, particularly in the rapidly growing portable
electronics industry. To illustrate this we present a
general-purpose, low-cost camera and image processing system in the
new packaging technology. This can be used in multimedia,
surveillance and smart vision applications. (7 Refs.)
Classification: B2250 (Multichip modules); B6210R (Multimedia
communications); B6140C (Optical information, image and video signal
processing); B7230 (Sensing devices and transducers); B6430H (Video
recording); B0170J (Product packaging)
Thesaurus: Consumer electronics; Image processing; Intelligent sensors;
Multichip modules; Multimedia systems; Surveillance; Video cameras
Free Terms: Low cost 3D packaging technology; Consumer applications;
System cost; Volume; Mass; Portable electronics industry; Low-cost
camera; Image processing system; Smart vision applications;
Surveillance applications; Multimedia applications; Multichip
module-vertical; Portable video communicator
Item Availability: CD-ROM.
INSPEC 5133644 B9601-2210-010
Doc Type: Journal Paper
Title: A novel type of low dielectric and heat-resistant resin
for printed wiring boards
Authors: Nawa, K.; Ohkita, M.
Affiliation: Sumitomo Metal Ind. R&D Center, Hyogo, Japan
Journal: IEEE Transactions on Components, Packaging and
Manufacturing Technology, Part B: Advanced Packaging
Vol: 18 Iss: 4 p. 691-6
Date: Nov. 1995
Country of Publication: USA
ISSN: 1070-9894 CODEN: IMTBE4
CCC: 1070-9894/95/$04.00
Language: English
Treatment: Application; New development; Practical; Experimental
Abstract: We developed a novel type of low dielectric and
heat-resistant resin. The resin was synthesized from dehydrating
reaction between fused aromatics and 1,4-benzenedimethanol,
therefore, it was called advanced polyCOndensed fused PolyNuclear
Aromatic Resin (advanced COPNA-Resin). The advanced COPNA-Resin
exhibited characteristic properties for an electrical insulator:
e.g., high Tg (250 degrees C), low dielectric constant (3.1 for 1
MHz), and low water absorption (0.37 wt.%). We studied fabrication
and properties of prepregs, double-sided copper-clad laminates,
printed wiring boards with copper-plated through-holes using advanced
COPNA-Resin as an insulating material. Prepregs were fabricated by
the dipping process of E-glass or T-glass fiber woven fabrics into
the resin solution. Copper-clad laminates were obtained by hot-press
fabrication of advanced COPNA-Resin prepregs. The laminates
reinforced by E-glass fiber woven fabric exhibited characteristic
properties for multilaying printed wiring boards. Tg was 255 degrees
C. The dielectric constant was 4.2. Advanced COPNA-Resin laminates
exhibited higher Tg and lower dielectric constant than polyimide
laminates known as heat-resistant and low dielectric materials. The
linear thermal expansion coefficient of advanced COPNA-Resin
laminates for xy-axis was 4-5 ppm, and that for z-axis was 29 ppm.
Advanced COPNA-Resin printed wiring board exhibited outstanding
reliability of electrical connection of copper-plated through-holes
in comparison with the epoxy or the polyimide system. From those
analysis for Tg, dielectric constant, linear thermal expansion
coefficients, and through-hole reliability, the advanced COPNA-Resin
was regarded as novel type of advanced material for high-density
interconnects such as fine-pitch surface mount and multichip modules.
(13 Refs.)
Classification: B2210 (Printed circuits); B0560 (Polymers and plastics
(engineering materials science)); B0550 (Composite materials
(engineering materials science)); B0170N (Reliability); B2830C
(Organic insulation); B2810 (Dielectric materials and properties)
Thesaurus: Circuit reliability; Hot pressing; Laminates; Materials
preparation; Organic insulating materials; Permittivity; Polymers;
Printed circuits; Surface mount technology; Thermal expansion
Free Terms: Low dielectric constant resin; Heat-resistant resin;
Printed wiring boards; Dehydrating reaction; Fused aromatics;
1,4-Benzenedimethanol; Polycondensed fused polynuclear aromatic
resin; Advanced COPNA-Resin; Low water absorption; Fabrication;
Prepregs; Double-sided Cu-clad laminates; Cu plated through-holes;
PTH PWB; MCM mounting; Fine-pitch SMD; High-density interconnects;
Through-hole reliability; Linear thermal expansion coefficients;
E-glass fiber woven fabric; Hot-pressing; Dipping process; 250 C; 255
C; Cu
Numerical Index: Temperature 5.23E+02 K; Temperature 5.28E+02 K
Chemical Index: Cu/int Cu/el
Item Availability: CD-ROM.
INSPEC 5118447 B9601-0170J-007 C9601-5490-001
Doc Type: Conference Paper
Title: Three dimensional stacking with diamond sheet heat
extraction for subnanosecond machine design
Authors: McDonald, J.F.; Greub, H.E.; Campbell, P.; Maier, C.;
Garg, A.; Steidl, S.
Affiliation: Rensselaer Polytech. Inst., Troy, NY, USA
Conf. Title: 1995 Proceedings. Seventh Annual IEEE International
Conference on Wafer Scale Integration (Cat.
No.95CH3574-2)
p. 62-71
Publisher: IEEE
New York, NY, USA
Date: 1995 ix+382 pp.
Country of Publication: USA
ISBN: 0 7803 2467 6
CCC: 0 7803 2466 8/95/$4.00
Language: English
Conf. Date: 18-20 Jan. 1995
Conf. Loc: San Francisco, CA, USA
Conf. Sponsor: IEEE Comput. Soc.; IEEE Components,
Packaging, & Manuf. Technol. Soc
Treatment: Practical
Abstract: Devices are becoming available whose inherent switching
speeds are approaching only a few picoseconds. CMOS FET devices with
0.12 micron channel length have exhibited f/sub T/ values of 89 GHz.
SiGe HBTs have been demonstrated with an f/sub T/ of 117 GHz.
InP/InGaAs/AlGaAs HBT's have exhibited an f/sub T/ of 200 GHz, with
minimum feature sizes that are above one micron. InGaAs/AlGaAs
MESFET's with 0.05 micron channel lengths have exhibited f/sub T/
values of 350 GHz. Clearly even faster devices are possible, and some
have even begun to appear in viable fabrication lines where prospects
for interesting levels of integration are being realized. For such
technologies subnanosecond machine cycles seem possible. However, for
conventional 2D chip or wafer fabrication some of the distances
between key components on these substrates can be too long for
subnanosecond operation. This may be true even for ideal transmission
line interconnections that exhibit 'speed of light' propagation
speeds and extremely wide bandwidths. At this point the last resort
is to shorten these interconnections by rearranging the components in
3D structures, implying either die or wafer stacking. This paper
explores some of the requirements for subnanosecond machine design,
and practical schemes to accomplish this with discussion on how to
distribute the power supply current and dissipate the heat generated.
These schemes use the full array of WSI, WSHP and MCM technologies
plus some new techniques for 3D vertical stacking. (0 Refs.)
Classification: B0170J (Product packaging); B2570 (Semiconductor
integrated circuits); C5490 (Other aspects of analogue and digital
computers)
Thesaurus: Cooling; Diamond; Heat sinks; Multichip modules; Wafer-scale
integration
Free Terms: Three dimensional stacking; Diamond sheet heat extraction;
Subnanosecond machine design; CMOS FET devices; SiGe HBTs;
InP/InGaAs/AlGaAs HBTs; InGaAs/AlGaAs MESFETs; Integration;
Transmission line interconnections; Die stacking; Wafer stacking;
Power supply current distribution; Vertical stacking; WSI; WSHP; MCM;
Switching speeds; Fabrication; C
Chemical Index: C/el
Item Availability: CD-ROM.
INSPEC 5112914 B9512-2570A-025 C9512-7410D-195
Doc Type: Conference Paper
Title: Chip-level thermal simulator to predict VLSI chip
temperature
Authors: Yi-Kan Cheng; Sung-Mo Kang
Affiliation: Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Conf. Title: 1995 IEEE Symposium on Circuits and Systems (Cat.
No.95CH35771)
p. 1392-5 vol.2
Publisher: IEEE
New York, NY, USA
Date: 1995 3 vol. l+2346 pp.
Country of Publication: USA
ISBN: 0 7803 2570 2
CCC: 0 7803 2570 2/95/$4.00
Language: English
Conf. Date: 28 April-3 May 1995
Conf. Loc: Seattle, WA, USA
Conf. Sponsor: IEEE Circuits & Syst. Soc
Treatment: Theoretical/Mathematical
Abstract: In this paper, a new thermal simulator is developed to
predict the steady-state and transient temperatures inside a VLSI
chip subjected to heating by single or multiple heat sources. It uses
a mixed 3D finite-difference and 1D analogous thermal circuit method,
taking into account any combination of boundary conditions, shape of
heat sources, and packaging. An analytical method is also presented
and compared to the numerical method. With this tool, the chip
temperature can be predicted accurately to provide design guidelines
for VLSI module placement and chip packaging. (5 Refs.)
Classification: B2570A (Integrated circuit modelling and process
simulation); B0170J (Product packaging); B0290P (Differential
equations); B1130B (Computer-aided circuit analysis and design);
C7410D (Electronic engineering computing); C4170 (Differential
equations)
Thesaurus: Circuit analysis computing; Finite difference methods;
Integrated circuit modelling; Integrated circuit packaging;
Temperature distribution; Thermal analysis; VLSI
Free Terms: Chip-level thermal simulator; VLSI chip temperature
prediction; Steady-state temperature; Transient temperature; Multiple
heat sources; Single heat source; 3D finite-difference method; 1D
analogous thermal circuit method; Analytical method; Numerical
method; Module placement; Chip packaging
Item Availability: CD-ROM.
INSPEC 5057087 B9511-0170J-016 C9511-7410D-033
Doc Type: Conference Paper
Title: Efficient reduced-order modeling of frequency-dependent
coupling inductances associated with 3-D interconnect
structures
Authors: Silveira, L.M.; Kamon, M.; White, J.
Affiliation: Res. Lab. of Electron., MIT, Cambridge, MA, USA
Conf. Title: Proceedings. The European Design and Test Conference.
ED&TC 1995 (Cat. No.95TH8058)
p. 534-8
Publisher: IEEE Comput. Soc. Press
Los Alamitos, CA, USA
Date: 1995 xxvii+611 pp.
Country of Publication: USA
ISBN: 0 8186 7039 8
CCC: 1066 1409/95/$4.00
Language: English
Conf. Date: 6-9 March 1995
Conf. Loc: Paris, France
Conf. Sponsor: IEEE Comput. Soc.; EDA Assoc.; Eur. Group
of TTC & the DATC; ACM/SIGDA
Treatment: Theoretical/Mathematical
Abstract: Reduced-order modeling techniques are now commonly used
to efficiently simulate circuits combined with interconnect, but
generating reduced-order models from realistic 3-D structures has
received less attention. In this paper we describe a Krylov-subspace
based method for deriving reduced-order models directly from the 3-D
magnetoquasistatic analysis program FASTHENRY. This new approach is
no more expensive than computing an impedance matrix at a single
frequency. (11 Refs.)
Classification: B0170J (Product packaging); B0290F (Interpolation and
function approximation); C7410D (Electronic engineering computing);
C4130 (Interpolation and function approximation)
Thesaurus: Electronic engineering computing; Inductance; Integrated
circuit interconnections; Integrated circuit packaging; Iterative
methods; Modelling; State-space methods
Free Terms: Reduced-order modeling; Frequency-dependent coupling
inductances; 3D interconnect structures; Krylov-subspace based
method; 3D magnetoquasistatic analysis program; FASTHENRY
Item Availability: CD-ROM.
INSPEC 5033354 B9510-0170J-024
Doc Type: Conference Paper in Journal
Title: Compliant bumps for adhesive flip-chip assembly
Authors: Keswick, K.; German, R.L.; Breen, M.; Nolan, R.
Affiliation: Microelectron. & Comput. Technol. Corp., Austin, TX, USA
Journal: IEEE Transactions on Components, Packaging and
Manufacturing Technology, Part B: Advanced Packaging
Vol: 18 Iss: 3 p. 503-10
Date: Aug. 1995
Country of Publication: USA
ISSN: 1070-9894 CODEN: IMTBE4
Language: English
Conf. Title: 44th Electronic Components and Technology Conference
Conf. Date: 1-4 May 1994
Conf. Loc: Washington, DC, USA
Treatment: Practical; Experimental
Abstract: Flip-chip-on-glass (FCOG) is susceptible to electrical
opens for a variety of reasons including, but not limited to,
movement in the Z-axis caused by flip-chip, adhesive CTE and water
absorption of the adhesive. Flip-chip assembly to co-fired ceramic
and laminate substrates suffers from these problems as well as
others, such as bow or twist in the substrate and bond pad height
irregularities. Success with adhesive flip-chip connections to these
substrates has, to date, been limited. Commercially available
adhesives have either failed to produce reliable bonds, or have
suffered from long cure time or a lack of reworkability. A solution
to these problems has been demonstrated by forming compliant bumps on
the chip or substrate bond pads using a photo-imagable polymer coated
with a thin layer of gold. Bumps 17 mu m tall with diameters between
17 mu m and 95 mu m have been fabricated and bonded. The resulting
compliant bump structure provides 30% of the bump height (5 mu m)
within the elastic compression range. This compliance eliminates many
of the demands placed on the assembly adhesives by other electrical
contacting methods (such as solid metal bumps or particles).
Compliant bumps allow the use of commercially available, fast curing,
easily reworkable adhesives for reliable flip-chip assembly. MCC's
compliant bumps have been mechanically cycled from minimum
compression (needed for electrical contact) to maximum compression
(based on diminishing compression distance versus applied force) 1000
times, with minimal degradation of the polymer core or metal
overcoat. Assemblies have been subjected to temperature cycling and
steam pot aging with substantial improvement in reliability when
compared to assemblies using solid metal bumps. Using compliant bump
technology, low temperature rework has been demonstrated with
compliant bumped chips on glass, laminate and MCM-C substrates. Chips
or substrates with compliant bumps are re-usable, a significant
advantage over conventional gold bump processes where the bump
structure is permanently deformed by the bonding process. (4 Refs.)
Classification: B0170J (Product packaging); B2240 (Microassembly
techniques); B0170E (Production facilities and engineering); B0170N
(Reliability); B2250 (Multichip modules)
Thesaurus: Ageing; Flip-chip devices; Integrated circuit reliability;
Life testing; Multichip modules; Tape automated bonding
Free Terms: Adhesive flip-chip assembly; Compliant bumps; Substrate
bond pads; Photoimagible polymer; Bump height; Elastic compression
range; Assembly adhesive; Reworkable adhesives; Compression distance;
Temperature cycling; Steam pot aging; Low temperature rework; Glass
substrates; Laminate substrates; MCM-C substrates; Bonding process;
17 To 95 micron
Numerical Index: Size 1.7E-05 to 9.5E-05 m
Item Availability: CD-ROM.
INSPEC 5027114 B9510-0170J-008
Doc Type: Conference Paper
Title: BGA inspection (Abstract)
Authors: Rideout, E.
Affiliation: RVSI, Hauppauge, NY, USA
Conf. Title: Sixteenth IEEE/CPMT International Electronics
Manufacturing Technology Symposium. 'Low-Cost
Manufacturing Technologies for Tomorrow's Global
Economy'. Proceedings 1994 IEMT Symposium (Cat.
No.94CH3473-6)
p. 388 vol.1
Publisher: IEEE
New York, NY, USA
Date: 1994 2 vol. (xii+404+viii+104 pp.)
Country of Publication: USA
ISBN: 0 7803 2037 9
CCC: 0 7803 2037 9/94/$3.00
Language: English
Conf. Date: 12-14 Sept. 1994
Conf. Loc: La Jolla, CA, USA
Conf. Sponsor: Electron. Ind. Assoc.; IEEE Components
Packaging & Manuf. Technol. Soc
Treatment: Practical; Experimental
Abstract: Summary form only give as follows. BGAs (Ball Grid
Arrays) have drawn much attention as the rising star of high-pincount
surface mount packaging technology. Compared to fine-pitch QFPs they
offer: a higher pincount for a given area, the ability to use
existing or at least less costly mounting equipment, and lower solder
defect rates. Disadvantages are a higher package cost and the
inability to inspect the solder joints after reflow. It has been
argued that the cost disadvantage goes away when overall
manufacturing costs through finished product are taken into account.
The problem of not being able to physically inspect the solder joints
may never go away. However, one can mitigate the need to inspect
solder joints by physical inspection of the BGA prior to mounting.
This paper discusses the physical attributes of a BGA which
contribute to poor mounting and how 3-D laser inspection can be used
to check those attributes. The presentation focuses on the use of a
laser system to measure coplanarity, true position error, pitch, ball
diameter, and board warpage. Also addressed are issues associated
with inspection of BGAs as presented to the placement system. Future
applications of 3-D inspection are mentioned. (0 Refs.)
Classification: B0170J (Product packaging); B0170L (Inspection and
quality control); B4360 (Laser applications)
Thesaurus: Inspection; Integrated circuit packaging; Laser beam
applications; Soldering; Surface mount technology
Free Terms: BGAs; Ball grid arrays; High-pincount surface mount
packaging technology; Mounting equipment; Solder defect rates;
Package cost; Solder joint inspection; 3D laser inspection;
Coplanarity; True position error; Ball diameter; Board warpage;
Placement system
Item Availability: CD-ROM.
INSPEC 5027113 B9510-0170J-007
Doc Type: Conference Paper
Title: 3-D packaging-applications of vertical multichip modules
(MCM-V) for microsystems
Authors: Val, C.
Affiliation: Thomson-CSF, Colombes, France
Conf. Title: Sixteenth IEEE/CPMT International Electronics
Manufacturing Technology Symposium. 'Low-Cost
Manufacturing Technologies for Tomorrow's Global
Economy'. Proceedings 1994 IEMT Symposium (Cat.
No.94CH3473-6)
p. 387 vol.1
Publisher: IEEE
New York, NY, USA
Date: 1994 2 vol. (xii+404+viii+104 pp.)
Country of Publication: USA
ISBN: 0 7803 2037 9
CCC: 0 7803 2037 9/94/$3.00
Language: English
Conf. Date: 12-14 Sept. 1994
Conf. Loc: La Jolla, CA, USA
Conf. Sponsor: Electron. Ind. Assoc.; IEEE Components
Packaging & Manuf. Technol. Soc
Treatment: Application; Practical
Abstract: Summary form only given. Classical 2-dimensional
interconnection is compared to microtechniques using the 3rd
dimension. Since 1989, several European projects with large companies
including Alcatel, Daimler-Benz, Geo-Marconi, SGS Thomson, and
several European universities, and Thomson-CSF have demonstrated,
evaluated, and qualified the 3-D technique. The results of
qualification are presented from 150 technology demonstrations plus
100 memory modules. The three-dimensional interconnection technology
is presented for five application groups. (0 Refs.)
Classification: B0170J (Product packaging); B2250 (Multichip modules)
Thesaurus: Integrated circuit interconnections; Integrated circuit
packaging; Multichip modules
Free Terms: 3D packaging; Vertical multichip modules; MCM-V;
Qualification; Memory modules; Technology demonstrations;
Three-dimensional interconnection technology
Item Availability: CD-ROM.
INSPEC 5022802 B9509-7220-019 C9509-5530-017
Doc Type: Conference Paper
Title: A micro-packaged image acquisition and processing module
Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, N.L.;
Shelley, A.J.
Affiliation: Sheffield Univ., UK
Conf. Title: Fifth International Conference on Image Processing and
its Applications (Conf. Publ. No.410)
p. 455-9
Publisher: IEE
London, UK
Date: 1995 xxii+857 pp.
Country of Publication: UK
ISBN: 0 85296 642 3
Language: English
Conf. Date: 4-6 July 1995
Conf. Loc: Edinburgh, UK
Treatment: Practical
Abstract: The paper describes a prototype module, which is an image
acquisition and processing pipeline implemented in a micro-package.
The module converts incident light directly to processed digital
video data. The system is packaged using a novel three-dimensional
technology called MCM-V (multichip module-vertical), Val (1991). This
technology stacks integrated circuits in the z-axis to produce dense
systems. The module is fully programmable and can be used in a wide
range of image processing tasks. The results presented form the first
stage in the development of high performance ultra-miniature camera
and image processing systems. (8 Refs.)
Classification: B7220 (Signal processing and conditioning equipment and
techniques); B1265F (Microprocessors and microcomputers); B2570
(Semiconductor integrated circuits); B0170J (Product packaging);
B2250 (Multichip modules); B6430H (Video recording); C5530 (Pattern
recognition and computer vision equipment); C5135 (Digital signal
processing chips); C5220P (Parallel architecture)
Thesaurus: Application specific integrated circuits; Digital signal
processing chips; Image processing equipment; Multichip modules;
Parallel architectures; Pipeline processing; Transputers; Video
cameras; Video signal processing; VLSI
Free Terms: Micro-packaged image acquisition; Processing module;
Prototype module; Processed digital video data; Three-dimensional
technology; MCM-V; Multichip module-vertical; Integrated circuits;
Z-axis; Dense systems; Fully programmable module; High performance
ultra-miniature camera
Item Availability: CD-ROM.
INSPEC 5022531 B9509-2560J-036
Doc Type: Conference Paper
Title: 3D FDTD analysis of a SOT353 package containing a bipolar
wideband cascode transistor using the compression
approach
Authors: Rittweger, M.; Werthen, M.; Kunisch, J.; Wolff, I.;
Chall, P.; Balm, B.; Lok, P.
Affiliation: Inst. fur Mobil-und Satellitenfunktechnik, Kamp-Lintfort,
Germany
Conf. Title: 1995 IEEE MTT-S International Microwave Symposium Digest
(Cat. No.95CH3577-4)
p. 1587-90 vol.3
Editors: Kirby, L.
Publisher: IEEE
New York, NY, USA
Date: 1995 3 vol. (lxxi+xli+1714 pp.)
Country of Publication: USA
ISBN: 0 7803 2581 8
CCC: CH3577-4/95/0000-1587$01.00
Language: English
Conf. Date: 16-20 May 1995
Conf. Loc: Orlando, FL, USA
Treatment: Theoretical/Mathematical
Abstract: A 3d electromagnetic simulation of an entire mold
injected plastic package including its coplanar environment is
presented. The active elements are substituted by inner ports. The
resulting network is connected with measured transistor data using a
circuit simulator. A comparison of the simulated data with measured
results is shown. The influence of the package and therefore the
meaning of such a simulation procedure is discussed. (5 Refs.)
Classification: B2560J (Bipolar transistors); B1350F (Solid-state
microwave circuits and devices); B0170J (Product packaging); B0290Z
(Other numerical methods)
Thesaurus: Finite difference time-domain analysis; Microwave bipolar
transistors; Plastic packaging; Semiconductor device packaging
Free Terms: 3D FDTD analysis; SOT353 package; Bipolar wideband cascode
transistor; Compression; Electromagnetic simulation; Mold injected
plastic package; Coplanar environment; Active elements; Inner ports;
Network; Circuit simulator
Item Availability: CD-ROM.
INSPEC 4999836 B9509-0170J-001
Doc Type: Journal Paper
Title: Thermal-mechanical enhanced high-performance silicone
gels and elastomeric encapsulants in microelectronic
packaging
Authors: Wong, C.P.
Affiliation: AT&T Bell Labs., Princeton, NJ, USA
Journal: IEEE Transactions on Components, Packaging, and
Manufacturing Technology, Part A
Vol: 18 Iss: 2 p. 270-3
Date: June 1995
Country of Publication: USA
ISSN: 1070-9886 CODEN: IMTAEZ
CCC: 1070-9886/95/$04.00
Language: English
Treatment: Application; Experimental
Abstract: A modern electronic device is a complex 3-D structure
that consists of millions of components for each single integrated
circuit (IC) chip. This complex and delicate device requires
effective encapsulation and packaging to ensure its long-term
reliability. This device encapsulant requires not only excellent
electrical and physical properties, but also suitable mechanical
properties for hostile and extreme temperature cycling requirements
(from -65 degrees to 150 degrees C). Hence, the mechanical and
thermal behavior of the encapsulant plays a critical role in device
reliability. Low stress encapsulants are the preferred choice for
microelectronic packaging. Silicone-based materials, either the
elastomers or gels, with their low modulus and excellent electrical
properties, are the best encapsulants. However, the intrinsic low
modulus silicone provides weak mechanic protection for the IC device.
We have, however, modified the silicone material with a high loading
of silica to improve its mechanical and physical properties. This
high-silica filler loading material improves not only its mechanical
property, but also its modulus. Furthermore, this modified high
modulus silicone material tends to have microcracks during the high
temperature thermal cycling testing that generates the device
reliability problem. In this paper, we will describe a modified
version of the thermal-mechanical enhanced silicone-based
encapsulant, its material formulation, curing process, thermal
mechanical failure and its protecting mechanisms, and its
application. (15 Refs.)
Classification: B0170J (Product packaging); B2220 (Integrated
circuits); B2570 (Semiconductor integrated circuits); B0170N
(Reliability); B0560 (Polymers and plastics (engineering materials
science))
Thesaurus: Encapsulation; Filled polymers; Gels; Integrated circuit
packaging; Integrated circuit reliability; Mechanical properties;
Polymer films; Silicones; Thermal stability; Thermal stress cracking;
Thermal stresses
Free Terms: Silicone gels; Elastomeric encapsulants; Microelectronic
packaging; Integrated circuit chip; Encapsulation; Mechanical
properties; Long-term reliability; Silica loaded material; High
modulus silicone material; Curing process; Thermal-mechanical
failure; Protecting mechanisms; Siloxane polymer; -65 To 150 C
Numerical Index: Temperature 2.08E+02 to 4.23E+02 K
Item Availability: CD-ROM.
INSPEC 4997899 B9508-6320-040
Doc Type: Conference Paper
Title: High density microwave packaging for T/R modules
Authors: Wooldridge, J.
Affiliation: Hughes Aircraft Co., El Segundo, CA, USA
Conf. Title: 1995 IEEE MTT-S International Microwave Symposium Digest
(Cat. No.95CH3577-4)
p. 181-4 vol.1
Editors: Kirby, L.
Publisher: IEEE
New York, NY, USA
Date: 1995 3 vol. (lxxi+xli+1714 pp.)
Country of Publication: USA
ISBN: 0 7803 2581 8
Language: English
Conf. Date: 16-20 May 1995
Conf. Loc: Orlando, FL, USA
Treatment: Application; Practical
Abstract: This paper describes the development of low cost 3-D
packaging of transmit/receive (T/R) modules for an active array radar
at X-band. The development focused on the design, manufacture and
interconnection of multi-layer aluminum nitride (AlN) substrates. The
substrates are electrically joined together with solderless
interconnects. All GaAs and most silicon chips have been flipped for
achieving low cost assembly and higher reliability. The major
microwave transmission line is conductor backed coplanar line CBCPW
which interfaces with the coplanar line used on the flipped microwave
chip. The interconnect technology is applicable to commercial high
speed data lines that are concerned about preserving the fast rise
time of the signal. (0 Refs.)
Classification: B6320 (Radar equipment, systems and applications);
B0170J (Product packaging); B2240 (Microassembly techniques); B0170E
(Production facilities and engineering)
Thesaurus: Coplanar waveguides; Electronic equipment manufacture;
Flip-chip devices; Integrated circuit interconnections;
Microassembling; Modules; Packaging; Phased array radar; Radar
equipment
Free Terms: High density microwave packaging; T/R modules; Low cost 3D
packaging; Transmit/receive modules; Active array radar; X-band;
Multilayer AlN substrates; Solderless interconnects; Flip-chip
assembly; Low cost assembly; Conductor backed coplanar line; Flipped
microwave chips; AlN; GaAs; Si
Chemical Index: AlN/sur Al/sur N/sur AlN/bin Al/bin N/bin; GaAs/int
As/int Ga/int GaAs/bin As/bin Ga/bin; Si/int Si/el
Item Availability: CD-ROM.
INSPEC 4955614 B9507-0170J-018
Doc Type: Conference Paper
Title: Preconditioning for multipole-accelerated 3-D inductance
extraction
Authors: Kamon, M.; White, J.
Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA,
USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.93TH0586-8)
p. 189-92
Publisher: IEEE
New York, NY, USA
Date: 1993 vii+238 pp.
Country of Publication: USA
ISBN: 0 7803 1427 1
CCC: 0 7803 1427 1/93/$3.00
Language: English
Conf. Date: 20-22 Oct. 1993
Conf. Loc: Monterey, CA, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc
Treatment: Theoretical/Mathematical
Abstract: Frequency-dependent inductances and resistances of
complicated 3-D packages can be extremely efficiently computed using
a volume-element formulation combined with a multipole-accelerated
iterative matrix solution method, provided the iterative method
converges rapidly. Two approaches to preconditioning the iterative
method are presented, and results are given which show that both
methods substantially accelerate iterative method convergence when
applied to the inductance extraction problem. (5 Refs.)
Classification: B0170J (Product packaging); B2570 (Semiconductor
integrated circuits); B0290F (Interpolation and function
approximation)
Thesaurus: Convergence of numerical methods; Inductance; Integrated
circuit packaging; Iterative methods; Matrix algebra
Free Terms: 3D packages; 3D inductance extraction; GMRES; Integrated
circuit; Frequency dependent resistance; Preconditioning;
Volume-element formulation; Multipole-accelerated iterative matrix
solution method; Iterative method convergence
Item Availability: CD-ROM.
INSPEC 4955599 B9507-5230-003
Doc Type: Conference Paper
Title: Efficient computation of ground plane inductances and
currents
Authors: Raghuram, R.; Divekar, D.; Wang, P.
Affiliation: CONTEC Microelectronics, San Jose, CA, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.93TH0586-8)
p. 131-4
Publisher: IEEE
New York, NY, USA
Date: 1993 vii+238 pp.
Country of Publication: USA
ISBN: 0 7803 1427 1
CCC: 0 7803 1427 1/93/$3.00
Language: English
Conf. Date: 20-22 Oct. 1993
Conf. Loc: Monterey, CA, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc
Treatment: Theoretical/Mathematical
Abstract: An efficient method for calculating an inductance
subcircuit from a 3-D geometry containing reference planes is
presented. The complexity is reduced to O(n/sup 2/log(n)) compared to
O(n/sup 6/) for a direct implementation. (6 Refs.)
Classification: B5230 (Electromagnetic compatibility and interference);
B0170J (Product packaging); B2570 (Semiconductor integrated circuits)
Thesaurus: Electric current; Electromagnetic interference; Fast Fourier
transforms; Inductance; Integrated circuit packaging; SPICE
Free Terms: Ground plane current; 3D geometry; SPICE; FFT; EMI;
Integrated circuits; Ground plane inductances; Inductance subcircuit
Item Availability: CD-ROM.
INSPEC 4955597 B9507-0170J-011
Doc Type: Conference Paper
Title: Exploiting symmetry in the extraction of electrical
packaging parameters
Authors: Huang, C.-C.
Affiliation: IBM Raleigh, Research Triangle Park, NC, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.93TH0586-8)
p. 125-7
Publisher: IEEE
New York, NY, USA
Date: 1993 vii+238 pp.
Country of Publication: USA
ISBN: 0 7803 1427 1
CCC: 0 7803 1427 1/93/$3.00
Language: English
Conf. Date: 20-22 Oct. 1993
Conf. Loc: Monterey, CA, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc
Treatment: Theoretical/Mathematical
Abstract: The author examines three different aspects of exploiting
a structure's symmetry to efficiently compute electrical packaging
parameters: (a) recognizing the cross-sectional symmetry eases the
numerical integration of 3-D partial inductances; (b) the direct
inversion of a partial impedance matrix lets one take advantage of a
structure's symmetry in computing resistance and inductance matrices
of uniformly coupled transmission lines; and (c) an almost symmetric
and/or periodic structure can be either decomposed or augmented to
exploit the special property of its corresponding system matrix.
(7 Refs.)
Classification: B0170J (Product packaging); B0290 (Numerical analysis)
Thesaurus: Electric impedance; Inductance; Integration; Matrix
inversion; Network parameters; Packaging; Skin effect; Symmetry
Free Terms: 3D partial inductance; Resistance matrix; CPV time; Skin
effect; Electrical packaging parameters; Cross-sectional symmetry;
Numerical integration; Direct inversion; Partial impedance matrix;
Inductance matrices; Uniformly coupled transmission lines; Periodic
structure; System matrix
Item Availability: CD-ROM.
INSPEC 4955589 B9507-0170J-010 C9507-7410D-015
Doc Type: Conference Paper
Title: A new three dimensional finite difference time domain
(3D-FDTD) simulator for modelling electronic
interconnections and packaging
Authors: Lu, L.X.; Wu, C.; Litva, J.
Affiliation: Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.93TH0586-8)
p. 92-5
Publisher: IEEE
New York, NY, USA
Date: 1993 vii+238 pp.
Country of Publication: USA
ISBN: 0 7803 1427 1
CCC: 0 7803 1427 1/93/$3.00
Language: English
Conf. Date: 20-22 Oct. 1993
Conf. Loc: Monterey, CA, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc
Treatment: Practical; Theoretical/Mathematical
Abstract: It has been shown that the finite difference time domain
(FDTD) method is an accurate and flexible technique to simulate
complex electromagnetic problems. A 3D-FDTD software package is
introduced. It can be used to simulate electronic packaging problems
from an electromagnetic field point of view. (3 Refs.)
Classification: B0170J (Product packaging); B1130B (Computer-aided
circuit analysis and design); B2570 (Semiconductor integrated
circuits); B2550F (Metallisation and interconnection technology);
C7410D (Electronic engineering computing)
Thesaurus: Circuit analysis computing; Circuit CAD; Finite difference
time-domain analysis; Integrated circuit interconnections; Integrated
circuit packaging
Free Terms: Electronic interconnections modelling; Three dimensional
finite difference time domain simulator; Electronic packaging
simulation; Electromagnetic problems; 3D-FDTD software package
Item Availability: CD-ROM.
INSPEC 4955579 B9507-1320-011
Doc Type: Conference Paper
Title: On the extraction of circuit parameters of microstrip
elements from MOM-Computed currents
Authors: Naishadham, K.
Affiliation: Dept. of Electr. Eng., Wright State Univ., Dayton, OH,
USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.93TH0586-8)
p. 50-2
Publisher: IEEE
New York, NY, USA
Date: 1993 vii+238 pp.
Country of Publication: USA
ISBN: 0 7803 1427 1
CCC: 0 7803 1427 1/93/$3.00
Language: English
Conf. Date: 20-22 Oct. 1993
Conf. Loc: Monterey, CA, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc
Treatment: Theoretical/Mathematical
Abstract: Microstrip circuit elements and discontinuities are
analyzed by an efficient moment method procedure that utilizes
closed-form Green's functions and exploits symmetries to fill the
moment matrix efficiently. Reciprocity is applied to derive a new
formula for computing the 'voltage' of a point on the microstrip
surface, which is used, along with the computed currents, to
calculate Z-parameters of the circuit elements. Computed circuit
parameters are compared with results obtained independently by the
least-squares Prony's method, and with measurements. (6 Refs.)
Classification: B1320 (Waveguide components); B1270D (Passive filters
and other passive networks); B1130B (Computer-aided circuit analysis
and design); B1310 (Waveguides)
Thesaurus: Circuit analysis computing; Green's function methods; Least
squares approximations; Method of moments; Microstrip circuits;
Microstrip discontinuities; Microstrip filters; S-parameters
Free Terms: Microstrip circuit elements; S-parameters; Circuit
simulation package; Reciprocity; Two-slot microstrip filter;
MOM-Computed currents; Discontinuities; Closed-form Green's
functions; Moment matrix; Microstrip surface; Z-parameters; Circuit
parameters; Least-squares Prony's method
Item Availability: CD-ROM.
INSPEC 4955575 B9507-0170J-004 C9507-7410D-009
Doc Type: Conference Paper
Title: Calculation of multi-port parameters of electronic
packages using a general purpose electromagnetics code
Authors: Rubin, B.J.; Daijavad, S.
Affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Conf. Title: Electrical Performance of Electronic Packaging (Cat.
No.93TH0586-8)
p. 37-9
Publisher: IEEE
New York, NY, USA
Date: 1993 vii+238 pp.
Country of Publication: USA
ISBN: 0 7803 1427 1
CCC: 0 7803 1427 1/93/$3.00
Language: English
Conf. Date: 20-22 Oct. 1993
Conf. Loc: Monterey, CA, USA
Conf. Sponsor: IEEE Microwave Theory & Tech. Soc
Treatment: Theoretical/Mathematical
Abstract: A powerful code developed by the authors to solve
radiation and scattering problems from arbitrary 3D
dielectric-conductor structures is modified to provide the terminal
characteristics of arbitrary package structures. By incorporating a
general de-embedding procedure to eliminate end effects, Y- and
S-parameters can be obtained for 3D transmission-line structures;
other parameters such as the C and L matrices can also be obtained.
Results for microstrip twin-tee and mesh-plane structures are
presented and compared with results already in the literature.
(8 Refs.)
Classification: B0170J (Product packaging); B1310 (Waveguides); B5240
(Transmission line theory); B1150F (Distributed linear networks);
B1130B (Computer-aided circuit analysis and design); C7410D
(Electronic engineering computing)
Thesaurus: Circuit analysis computing; Microstrip lines; Multiport
networks; Packaging; S-parameters; Transmission line matrix methods
Free Terms: C matrices; Microstrip twin-tee structures; Multiport
parameters; Radiation problems Y-parameters; Electronic packages;
General purpose electromagnetics code; Scattering problems; Arbitrary
3D dielectric-conductor structures; Terminal characteristics; General
de-embedding procedure; End effects; S-parameters; 3D
transmission-line structures; L matrices; Mesh-plane structures
Item Availability: CD-ROM.
INSPEC 4946055 C9506-4230M-037
Doc Type: Conference Paper
Title: Scalable architectures with k-ary n-cube cluster-c
organization
Authors: Basak, D.; Panda, D.K.
Affiliation: Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus,
OH, USA
Conf. Title: Proceedings of the Fifth IEEE Symposium on Parallel and
Distributed Processing (Cat. No.93TH0584-3)
p. 780-7
Publisher: IEEE Comput. Soc. Press
Los Alamitos, CA, USA
Date: 1993 xviii+823 pp.
Country of Publication: USA
ISBN: 0 8186 4222 X
CCC: 1063-6374/93/$03.00
Language: English
Conf. Date: 1-4 Dec. 1993
Conf. Loc: Dallas, TX, USA
Conf. Sponsor: IEEE
Treatment: Theoretical/Mathematical
Abstract: Recent advancements in VLSI and packaging technologies
demonstrate attractiveness in building scalable parallel systems
using clustered configurations while exploiting communication
locality. Clustered architectures using buses or MINs as the
inter-cluster interconnection do not satisfy both the above
objectives. This paper proposes a new class of k-ary n-cube cluster-c
scalable architectures by combining the scalability of k-ary n-cube
wormhole-routed networks with the cost-effectiveness of processor
cluster designs. This paper focuses on direct cluster
interconnection. The interplay between various system parameters and
routing schemes are analyzed to determine optimal configurations
under the constant bisection bandwidth constraint. Our analysis
indicates that small sized clusters with a ring intra-cluster
topology and a 2D/3D/4D inter-cluster network connecting these
clusters offer best system performance. (15 Refs.)
Classification: C4230M (Multiprocessor interconnection); C5220P
(Parallel architecture)
Thesaurus: Multiprocessor interconnection networks; Parallel
architectures
Free Terms: Scalable parallel systems; Clustered configurations;
Communication locality; Inter-cluster interconnection; K-ary n-cube
cluster-c scalable architectures; K-ary n-cube wormhole-routed
networks; Processor cluster designs; Direct cluster interconnection;
Constant bisection bandwidth constraint
Item Availability: CD-ROM.
INSPEC 4938869 B9506-2250-013
Doc Type: Conference Paper
Title: Impact of low-cost MCM-D on MCM designers' technology
choices
Authors: Ho, C.W.; Green, H.
Affiliation: MicroModule Syst., Inc., Cupertino, CA, USA
Conf. Title: Fifteenth IEEE/CHMT International Electronics
Manufacturing Technology Symposium (Cat. No.93CH3355-5)
p. 481-3
Publisher: IEEE
New York, NY, USA
Date: 1993 xii+504 pp.
Country of Publication: USA
ISBN: 0 7803 1424 7
CCC: 0 7803 1424 7/93/$3.00
Language: English
Conf. Date: 4-6 Oct. 1993
Conf. Loc: Santa Clara, CA, USA
Conf. Sponsor: Electron. Ind. Assoc.; Components, Hybrids
& Manuf. Technol. Soc
Treatment: General/Review
Abstract: Multichip module (MCM)-D has been portrayed as the
technology with the most promise, the greatest ability to handle high
clock frequencies, and the long-term choice for high-performance
applications - although always with a warning that MCM-D was many
times more expensive a technology choice than MCM-L. These
assumptions are rapidly becoming invalid. MCM-D performance has
emerged as foreseen, but at the same time prices for completed
modules have fallen greatly. Economics of scale have allowed MCM-D
manufacturers to take advantage of their technology by building
products that only MCM-D line geometries and form factors make
possible. In addition, any enabling technology - like 3-D memory or
3-D stacking of MCM's - for MCM-L will also be usable to equal or
greater effect by MCM-D. MCM applications are continuing to follow
long-term industry trends for higher performance, lower costs, and
smaller form factors. (4 Refs.)
Classification: B2250 (Multichip modules); B0170J (Product packaging)
Thesaurus: Economics; Integrated circuit design; Integrated circuit
interconnections; Integrated circuit manufacture; Integrated circuit
packaging; Integrated circuit yield; Multichip modules
Free Terms: MCM design; Volume applications; Low-cost MCM-D; Technology
choices; Performance; Enabling technology; 3-D memory; 3-D stacking;
Smaller form factors
Item Availability: CD-ROM.
INSPEC 4918595 B9505-0170J-035
Doc Type: Journal Paper
Title: Analysis of TAB inner lead fatigue in thermal cycle
environments
Authors: Cluff, K.D.
Affiliation: Air Transp. Syst. Div., Honeywell Inc., Phoenix, AZ, USA
Journal: IEEE Transactions on Components, Packaging, and
Manufacturing Technology, Part A
Vol: 18 Iss: 1 p. 101-7
Date: March 1995
Country of Publication: USA
ISSN: 1070-9886 CODEN: IMTAEZ
CCC: 1070-9886/95/$04.00
Language: English
Treatment: Practical; Theoretical/Mathematical
Abstract: The inner leads of a Tape Automated Bonding (TAB) device
can be subject to early fatigue failures in thermal cycle
environments. This paper describes a 3-D nonlinear finite clement
analysis of the failure mechanism, and verifies the results by
experiment. Some TAB applications require environmental qualification
and electrical testing in the unexcised tape carrier or retain a
significant portion of the polyimide tape in the assembly. In these
cases the Coefficient of Thermal Expansion (CTE) mismatch between the
silicon die and polyimide tape can cause plastic strains in the inner
leads. Several design variations are quantified. Those with first
order effects were found to be encapsulant material, lead length, and
lead material. (8 Refs.)
Classification: B0170J (Product packaging); B2240 (Microassembly
techniques); B0170N (Reliability); B0290T (Finite element analysis)
Thesaurus: Encapsulation; Environmental testing; Failure analysis;
Fatigue; Finite element analysis; Integrated circuit packaging; Lead
bonding; Plastic deformation; Tape automated bonding; Thermal
expansion
Free Terms: TAB inner lead fatigue; Thermal cycle environments; Fatigue
failures; 3D nonlinear finite clement analysis; Failure mechanism;
Environmental qualification; Electrical testing; Unexcised tape
carrier; Polyimide tape; Coefficient of thermal expansion; CTE
mismatch; Plastic strains; Design variations; First order effects;
Encapsulant material; Lead length; Lead material
Item Availability: CD-ROM.
INSPEC 4898227 B9504-1130B-052 C9504-7410D-141
Doc Type: Journal Paper
Title: A 3-D electromagnetic simulator for high frequency
applications
Authors: Jian-X. Zheng
Affiliation: Zeland Software Inc., Fremont, CA, USA
Journal: IEEE Transactions on Components, Packaging and
Manufacturing Technology, Part B: Advanced Packaging
Vol: 18 Iss: 1 p. 112-18
Date: Feb. 1995
Country of Publication: USA
ISSN: 1070-9894 CODEN: IMTBE4
CCC: 1070-9894/95/$04.00
Language: English
Treatment: Application; Practical; Theoretical/Mathematical
Abstract: A general purpose full-wave electromagnetic simulator
IE3-D has been developed for the analysis and design of
high-frequency and high-speed electronic circuit structures. For an
arbitrarily shaped 3-D metallic layered structure, the integral
equation, and method of moment-based simulator solves the current
distribution on the structure expanded into roof-top functions on a
set of 3-D triangular and rectangular cells. The circuit parameters
are extracted from the solved current distribution in the form of
either S-parameters frequency response and RLC-equivalent circuit in
SPICE format. (15 Refs.)
Classification: B1130B (Computer-aided circuit analysis and design);
B0290R (Integral equations); B1350 (Microwave circuits and devices);
B1265 (Digital electronics); B0170J (Product packaging); C7410D
(Electronic engineering computing); C6185 (Simulation techniques);
C4180 (Integral equations)
Thesaurus: Circuit analysis computing; Current distribution; Digital
circuits; Digital simulation; Equivalent circuits; Frequency
response; Integral equations; Method of moments; Microwave circuits;
Packaging; S-parameters; SPICE
Free Terms: 3D electromagnetic simulator; High frequency applications;
Full-wave EM simulator; IE3-D; High-speed electronic circuits;
Integral equation; Method of moment-based simulator; Current
distribution; Roof-top functions; 3D rectangular cells; 3D triangular
cells; Circuit parameters; S-parameters frequency response;
RLC-equivalent circuit; SPICE format
Item Availability: CD-ROM.
INSPEC 4898224 B9504-1130B-051 C9504-7410D-140
Doc Type: Journal Paper
Title: Algorithms for coupled transient simulation of circuits
and complicated 3-D packaging
Authors: Silveira, L.M.; Kamon, M.; White, J.
Affiliation: Res. Lab. of Electron., MIT, Cambridge, MA, USA
Journal: IEEE Transactions on Components, Packaging and
Manufacturing Technology, Part B: Advanced Packaging
Vol: 18 Iss: 1 p. 92-8
Date: Feb. 1995
Country of Publication: USA
ISSN: 1070-9894 CODEN: IMTBE4
CCC: 1070-9894/95/$04.00
Language: English
Treatment: Theoretical/Mathematical
Abstract: Techniques are described for coupled simulation of
complicated 3-D interconnect and nonlinear transistor drivers and
receivers. The approach is based on combining: multipole-accelerated
method-of-moments techniques for extracting frequency-dependent
inductances and resistances for the interconnect; a sectioning method
for fitting the frequency-domain data with a rational function; a
balanced-realization approach to reducing the order of the rational
function in a guaranteed stable manner; and an implementation of fast
recursive convolution to incorporate the rational function in SPICE3.
Results are presented to demonstrate some of the frequency-dependent
effects in a packaging analysis problem. (13 Refs.)
Classification: B1130B (Computer-aided circuit analysis and design);
B0170J (Product packaging); B0290Z (Other numerical methods); C7410D
(Electronic engineering computing); C4190 (Other numerical methods)
Thesaurus: Circuit analysis computing; Convolution; Distributed
parameter networks; Driver circuits; Inductance; Integrated circuit
interconnections; Method of moments; Packaging; SPICE; Transient
analysis
Free Terms: Coupled transient simulation; 3D packaging; Nonlinear
transistor drivers; Nonlinear transistor receivers;
Multipole-accelerated moment methods; Method-of-moments techniques;
Frequency-dependent inductances; Frequency-dependent resistances;
Interconnect; Sectioning method; Frequency-domain data; Rational
function; Balanced-realization approach; Fast recursive convolution;
SPICE3; Packaging analysis problem
Item Availability: CD-ROM.
INSPEC 4886241 B9504-2570A-007 C9504-7410D-063
Doc Type: Conference Paper
Title: Layout-based extraction of IC electrical behavior models
Authors: Wang, K.; Rotella, F.; Chen, T.; Yang, D.; Lee, A.; Yu,
Z.; Knepper, R.W.; Watt, J.; Dutton, R.W.
Affiliation: Center for Integrated Syst., Stanford Univ., CA, USA
Conf. Title: International Electron Devices Meeting 1994. Technical
Digest (Cat. No.94CH35706)
p. 209-12
Publisher: IEEE
New York, NY, USA
Date: 1994 947 pp.
Country of Publication: USA
ISBN: 0 7803 2111 1
CCC: 0 7803 2111 1/94/$4.00
Language: English
Conf. Date: 11-14 Dec. 1994
Conf. Loc: San Francisco, CA, USA
Conf. Sponsor: Electron Devices Soc. IEEE
Treatment: Application; Theoretical/Mathematical
Abstract: Behavior of IC structures is modeled using a
heterogeneous set of tools and derived physical representations. A
unified 3D information model is demonstrated with special emphasis on
application of solid geometry modeling techniques. Examples used in
this presentation include modeling of SRAM technology and
interconnect structures that include packaging considerations as
well. Issues of mixed level simulations are considered based on
circuit and thermal constraints on IC structures. (3 Refs.)
Classification: B2570A (Integrated circuit modelling and process
simulation); B1130B (Computer-aided circuit analysis and design);
C7410D (Electronic engineering computing)
Thesaurus: Circuit analysis computing; Circuit CAD; Integrated circuit
interconnections; Integrated circuit layout; Integrated circuit
modelling; Integrated circuit packaging; SRAM chips
Free Terms: Layout-based extraction; IC electrical behavior models;
Unified 3D information model; Solid geometry modeling techniques;
SRAM technology; Interconnect structures; Packaging considerations;
Mixed level simulations
Item Availability: CD-ROM.
INSPEC 4874636 B9503-0170J-062 C9503-7410D-107
Doc Type: Conference Paper
Title: Algorithms for coupled transient simulation of circuits
and complicated 3-D packaging
Authors: Silveira, L.M.; Kamon, M.; White, J.
Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA,
USA
Conf. Title: 1994 Proceedings. 44th Electronic Components and
Technology Conference (Cat. No.94CH3241-7)
p. 962-70
Publisher: IEEE
New York, NY, USA
Date: 1994 xvii+1118 pp.
Country of Publication: USA
ISBN: 0 7803 0914 6
CCC: 0569-5503/94/0000-0962$3.00
Language: English
Conf. Date: 1-4 May 1994
Conf. Loc: Washington, DC, USA
Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol.
Soc.; Electron. Ind. Assoc
Treatment: Theoretical/Mathematical
Abstract: In this paper techniques are described for coupled
simulation of complicated 3-D interconnect and nonlinear transistor
drivers and receivers. The approach is based on combining:
multipole-accelerated method-of-moments techniques for extracting
frequency-dependent inductances and resistances for the interconnect;
a sectioning method for fitting the frequency-domain data with a
rational function; a balanced-realization approach to reducing the
order of the rational function in a guaranteed stable manner; and an
implementation of fast recursive convolution to incorporate the
rational function in SPICE3. Results are presented to demonstrate
some of the frequency-dependent effects in a packaging analysis
problem. (13 Refs.)
Classification: B0170J (Product packaging); B1130B (Computer-aided
circuit analysis and design); C7410D (Electronic engineering
computing)
Thesaurus: Circuit analysis computing; Digital simulation; Driver
circuits; Method of moments; Packaging; SPICE; Transient analysis
Free Terms: Coupled transient simulation; 3D packaging; 3D
interconnect; Nonlinear transistor drivers; Nonlinear transistor
receivers; Multipole-accelerated moment method; Frequency-dependent
inductances; Frequency-dependent resistances; Sectioning method;
Frequency-domain data; Rational function; Balanced-realization
approach; Fast recursive convolution; SPICE3; Packaging analysis
problem; Frequency-dependent effects
Item Availability: CD-ROM.
INSPEC 4874605 B9503-0170J-051
Doc Type: Conference Paper
Title: Impact of moisture/reflow induced delaminations on
integrated circuit thermal performance
Authors: Conrad, T.R.; Shook, R.L.
Affiliation: AT&T Bell Labs., Allentown, PA, USA
Conf. Title: 1994 Proceedings. 44th Electronic Components and
Technology Conference (Cat. No.94CH3241-7)
p. 527-31
Publisher: IEEE
New York, NY, USA
Date: 1994 xvii+1118 pp.
Country of Publication: USA
ISBN: 0 7803 0914 6
CCC: 0569-5503/94/0000-0527$3.00
Language: English
Conf. Date: 1-4 May 1994
Conf. Loc: Washington, DC, USA
Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol.
Soc.; Electron. Ind. Assoc
Treatment: Practical; Theoretical/Mathematical; Experimental
Abstract: Ambient moisture uptake in plastic surface mount IC
packages can cause delamination of critical internal surfaces within
the package during reflow assembly. Delaminations can result in
reduced thermal cycling life performance or provide for a pathway for
the ingress of chemicals and contaminates. The effects that
moisture/reflow induced delaminations can have on the thermal
performance of plastic packaged ICs are not entirely understood. In
this paper, the thermal performance of moisture/reflow delaminated
ICs is reported. The effective sensitivity of the thermal performance
as a result of the moisture/reflow induced delaminations was measured
by experimental thermal resistance measurements ( theta /sub JA/) and
compared to theoretical calculations based on Finite Element Analysis
(FEA). Both 3-D and 2-D FEA models were developed for predictive
responses which gave excellent correlation to the experimental
measurements. The results showed that interfacial delaminations can
cause a measurable increase in theta /sub JA/. The magnitude of the
increase is found to be proportional to the power consumption of the
device and dependent on the delamination gap thickness. Expected
reliability degradation as a result of die temperature rise from the
interfacial delaminations is most significant for plastic packaged
devices of power ratings greater than about 1 W. (15 Refs.)
Classification: B0170J (Product packaging); B2240 (Microassembly
techniques); B0170N (Reliability); B0290T (Finite element analysis)
Thesaurus: Delamination; Finite element analysis; Integrated circuit
packaging; Integrated circuit reliability; Life testing;
Microassembling; Moisture; Plastic packaging; Reflow soldering;
Surface mount technology; Thermal resistance
Free Terms: Moisture/reflow induced delaminations; Integrated circuit
thermal performance; Ambient moisture uptake; Plastic surface mount
IC packages; Critical internal surfaces; Reflow assembly; Thermal
cycling life performance; Thermal resistance measurements; Finite
element analysis; Predictive responses; Power consumption;
Delamination gap thickness; Reliability degradation; Die temperature
rise; Power ratings
Item Availability: CD-ROM.
INSPEC 4868835 B9503-5230-021
Doc Type: Conference Paper
Title: Heatsink radiation as a function of geometry
Authors: Brench, C.E.
Affiliation: Digital Equipment Corp., Maynard, MA, USA
Conf. Title: Chicago 1994. Compatibility in the Loop. IEEE
International Symposium on EMC. Symposium Record (Cat.
No.94CH3347-2)
p. 105-9
Publisher: IEEE
New York, NY, USA
Date: 1994 xi+514 pp.
Country of Publication: USA
ISBN: 0 7803 1398 4
CCC: 0 7803 1398 4/94/0000-0018$4.00
Language: English
Conf. Date: 22-26 Aug. 1994
Conf. Loc: Chicago, IL, USA
Treatment: Practical; Experimental
Abstract: In today's high performance computers the need to cool
the CPU and other VLSI devices with attached heatsinks is very
common. The heatsink geometry is usually driven by the thermal
requirements in conjunction with the device packaging needs. As the
processor speeds increase the die power dissipation also increases,
leading to an increase in the preferred heatsink size. In this paper
the variations in the radiation characteristics of heatsinks are
examined with respect to their geometries by use of a three
dimensional finite difference time domain (FDTD) technique. (3 Refs.)
Classification: B5230 (Electromagnetic compatibility and interference);
B0170J (Product packaging); B2570 (Semiconductor integrated
circuits); B0290Z (Other numerical methods)
Thesaurus: Electromagnetic interference; Finite difference time-domain
analysis; Heat sinks; Packaging; VLSI
Free Terms: High performance computers; CPU; VLSI devices; Heatsink
geometry; Processor speeds; Thermal requirements; Packaging; Die
power dissipation; Heatsink size; Heatsink radiation characteristics;
Finite difference time domain; 3D FDTD
Item Availability: CD-ROM.
INSPEC 4858568 B9502-0170J-030
Doc Type: Conference Paper
Title: Compliant bumps for adhesive flip chip assembly
Authors: Keswick, K.; German, R.; Breen, M.; Nolan, R.
Affiliation: MCC, Austin, TX, USA
Conf. Title: 1994 Proceedings. 44th Electronic Components and
Technology Conference (Cat. No.94CH3241-7)
p. 7-15
Publisher: IEEE
New York, NY, USA
Date: 1994 xvii+1118 pp.
Country of Publication: USA
ISBN: 0 7803 0914 6
CCC: 0569-5503/94/0000-0007$3.00
Language: English
Conf. Date: 1-4 May 1994
Conf. Loc: Washington, DC, USA
Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol.
Soc.; Electron. Ind. Assoc
Treatment: Practical; Experimental
Abstract: Flip-chip-on-glass (FCOG) is susceptible to electrical
opens for a variety of reasons including, but not limited to,
movement in the z-axis caused by flip chip adhesive CTE and water
absorption of the adhesive. Flip chip assembly to cofired ceramic and
laminate substrates suffers from these problems as well as others,
such as bow or twist in the substrate and bond pad height
irregularities. Success with adhesive flip chip connections to these
substrates has, to date, been limited. Commercially available
adhesives have either failed to produce reliable bonds, or have
suffered from long cure time or a lack of reworkability. A solution
to these problems has been demonstrated by forming compliant bumps on
the chip or substrate bond pads using a photoimagible polymer coated
with a thin layer of gold. Bumps 17 mu m tall with diameters between
17 mu m and 95 mu m have been fabricated and bonded. The resulting
compliant bump structure provides 30% of the bump height (5 mu m)
within the elastic compression range. This compliance eliminates many
of the demands placed on the assembly adhesives by other electrical
contacting methods (such as solid metal bumps or particles).
Compliant bumps allow the use of commercially available, fast curing,
easily reworkable adhesives for reliable flip chip assembly.
(0 Refs.)
Classification: B0170J (Product packaging); B2240 (Microassembly
techniques); B0170N (Reliability)
Thesaurus: Adhesion; Flip-chip devices; Integrated circuit
interconnections; Integrated circuit packaging; Integrated circuit
reliability; Lead bonding
Free Terms: Compliant bumps; Adhesive flip chip assembly;
Flip-chip-on-glass; Electrical opens; Flip chip adhesive CTE; Water
absorption; Ceramic substrates; Laminate substrates; Bond pad height
irregularities; Bow; Twist; Photoimagible polymer; Elastic
compression range; Curing; Reworkable adhesives; 17 To 95 micron
Numerical Index: Size 1.7E-05 to 9.5E-05 m
Item Availability: CD-ROM.
INSPEC 4857591 C9502-1290-030
Doc Type: Conference Paper
Title: Hybrid genetic algorithm for container packing in three
dimensions
Authors: Lin, J.-L.; Foote, B.; Pulat, S.; Chang, C.-H.; Cheung,
J.Y.
Affiliation: Oklahoma Univ., USA
Conf. Title: Proceedings. The Ninth Conference on Artificial
Intelligence for Applications (Cat. No.93CH3254-0)
p. 353-9
Publisher: IEEE Comput. Soc. Press
Los Alamitos, CA, USA
Date: 1993 xvi+471 pp.
Country of Publication: USA
ISBN: 0 8186 3840 0
CCC: 1043-0989/93/$03.00
Language: English
Conf. Date: 1-5 March 1993
Conf. Loc: Orlando, FL, USA
Conf. Sponsor: IEEE Comput. Soc. Tech. Committee on
Pattern Analysis & Mach. Intelligence; AAAI;
Canadian Soc. Comput. Stud. Intelligence
Treatment: Theoretical/Mathematical
Abstract: The concept of genetics using multiple-chromosomes is
applied to a 3D container packing problem. The 3D packing problem
deals with packing a given set of regular shaped boxes of different
sizes and weights into larger containers. The algorithm must seek to
minimize the wasted space under a constraint: the heavier and the
larger boxes must be placed below the lighter ones. The present
emphasis is to find a good solution quickly by heuristic means. A set
of heuristic rules is incorporated into the genetic algorithm (GA)
approach to aid in optimization. This hybrid GA yields an
optimization algorithm that outperforms either of the parts. The
simulation results showed that the new algorithm has better
adaptivity for large problems and near optimal solutions for small
problems. (40 Refs.)
Classification: C1290 (Applications of systems theory); C1180
(Optimisation techniques); C1230 (Artificial intelligence)
Thesaurus: Genetic algorithms; Heuristic programming; Operations
research; Packaging
Free Terms: Hybrid genetic algorithm; Box size; Box weight; Wasted
space minimization; Multiple-chromosomes; 3D container packing
problem; Regular shaped boxes; Heuristic rules; Optimization
algorithm; Simulation; Adaptivity; Near optimal solutions
Item Availability: CD-ROM.
INSPEC 4854347 B9502-1350H-011
Doc Type: Journal Paper
Title: A design technique for a 60 GHz-bandwidth distributed
baseband amplifier IC module
Authors: Shibata, T.; Kimura, S.; Kimura, H.; Imai, Y.; Umeda, Y.;
Akazawa, Y.
Affiliation: NTT LSI Labs., Kanagawa, Japan
Journal: IEEE Journal of Solid-State Circuits
Vol: 29 Iss: 12 p. 1537-44
Date: Dec. 1994
Country of Publication: USA
ISSN: 0018-9200 CODEN: IJSCBC
CCC: 0018-9200/94/$04.00
Language: English
Treatment: Practical
Abstract: A DC-60 GHz, 9 dB distributed amplifier IC module is
fabricated with 0.15 mu m InAlAs-InGaAs low-noise HEMTs with 155 GHz
f/sub T/ and 234 GHz f/sub max/. The device is mounted in a metal
package with 1.8 mm coaxial cable signal interfaces. The package is
specially designed using three-dimensional electromagnetic field
analyses, resulting in very flat frequency characteristics of the
module within 1.5 dB gain ripples over the entire bandwidth. A
multichip module loaded with two amplifier ICs in cascade is also
fabricated, and operates at a 17.5 dB gain from 60 kHz to 48 GHz. The
1 dB gain compression output power is about 5 dBm for both modules.
The noise figure of the single-chip module is approximately 4 dB over
a 10-40 GHz frequency range. (7 Refs.)
Classification: B1350H (Microwave integrated circuits); B1220
(Amplifiers); B2570H (Other field effect integrated circuits); B2250
(Multichip modules); B0170J (Product packaging)
Thesaurus: Coplanar waveguides; Distributed amplifiers; Field effect
MIMIC; HEMT integrated circuits; Integrated circuit packaging;
Millimetre wave amplifiers; Multichip modules; Wideband amplifiers
Free Terms: Design technique; Distributed baseband amplifier; Amplifier
IC module; Low-noise HEMTs; Metal package; Coaxial cable signal
interfaces; Three-dimensional EM field analyses; 3D electromagnetic
field analyses; Multichip module; Cascaded amplifiers; Single-chip
module; MCM; MIMIC; MM-wave IC; 60 GHz; 0 To 60 GHz; 0.15 Micron; 9
DB; 17.5 DB; 4 DB; InAlAs-InGaAs
Numerical Index: Bandwidth 6.0E+10 Hz; Frequency 0.0E+00 to 6.0E+10 Hz;
Size 1.5E-07 m; Gain 9.0E+00 dB; Gain 1.75E+01 dB; Noise figure
4.0E+00 dB
Chemical Index: InAlAs-InGaAs/int InAlAs/int InGaAs/int Al/int As/int
Ga/int In/int InAlAs/ss InGaAs/ss Al/ss As/ss Ga/ss In/ss
Item Availability: CD-ROM.
INSPEC 4852710 B9502-7630-039 C9502-7460-041
Doc Type: Conference Paper
Title: High-performance, AMLCD-based 'smart' display for the
Space Shuttle glass cockpit
Authors: Thomsen, S.V.; Hancock, W.R.
Affiliation: Satellite Syst. Oper., Honeywell Inc., Glendale, AZ, USA
Conf. Title: AIAA/IEEE Digital Avionics Systems Conference. 13th DASC
(Cat. No.94CH3573-0)
p. 281-8
Publisher: IEEE
New York, NY, USA
Date: 1994 639 pp.
Country of Publication: USA
ISBN: 0 7803 2425 0
CCC: 0 7803 2425 0/94/$4.00
Language: English
Conf. Date: 30 Oct.-3 Nov. 1994
Conf. Loc: Phoenix, AZ, USA
Treatment: Practical
Abstract: A production program is underway for an Active Matrix
Liquid Crystal Display (AMLCD) for the National Aeronautics and Space
Administration (NASA) Space Shuttle glass cockpit upgrade. A 'smart'
display architecture is used with a powerful Reduced Instruction Set
Computer (RISC) processing element and custom graphics accelerator
that can render two- and three-dimensional (2-D and 3-D), fully
anti-aliased graphical images at 30 Hz update rates. In addition, the
Multifunction Display Unit (MDU) can display external NTSC/RS-170
video to crew members, or output an NTSC signal for repeater monitor
requirements. The unit is a very compact design-minimizing volume,
weight, and power. Advanced AMLCD technology delivers exceptional
brightness, gray-scale performance, off-axis viewing, and dynamic
image response across the full 6.71*6.71 in. active display area.
High resolution is achieved with 1152*1152 color dots and 28 shades
of gray per primary color. Exceptional imaging quality, throughput,
graphics generation, and reliability all combine to produce a display
package that greatly enhances flight-deck performance. (3 Refs.)
Classification: B7630 (Avionic systems and aerospace instrumentation);
B4150D (Liquid crystal devices); B7260 (Display technology and
systems); C7460 (Aerospace engineering computing); C5220 (Computer
architecture)
Thesaurus: Aerospace computing; Computer architecture; Liquid crystal
displays; Reduced instruction set computing; Space vehicle
electronics; Special purpose computers
Free Terms: Smart display; Space Shuttle glass cockpit; Production
program; Active matrix liquid crystal display; Packaging; NASA;
Reduced Instruction Set Computer; RISC; Custom graphics accelerator;
Antialiased graphical images; Multifunction Display Unit;
NTSC/RS-170; Design-minimizing volume; Brightness; Gray-scale
performance; Off-axis viewing; Dynamic image response; Active display
area; Color dots; Imaging quality; Throughput; Graphics generation
Item Availability: CD-ROM.
INSPEC 4846877 B9502-0170J-005 C9502-7410D-031
Doc Type: Conference Paper
Title: Efficient three-dimensional LCR extraction and modeling
of VLSI packages
Authors: Specks, J.W.
Affiliation: Microcontroller Design Center, Motorola Inc., Munich,
Germany
Conf. Title: Proceedings of the 36th Midwest Symposium on Circuits and
Systems (Cat. No.93CH3381-1)
p. 1166-9 vol.2
Publisher: IEEE
New York, NY, USA
Date: 1993 2 vol. xxxv+1565 pp.
Country of Publication: USA
ISBN: 0 7803 1760 2
CCC: CH3381-1/93/$01.00
Language: English
Conf. Date: 16-18 Aug. 1993
Conf. Loc: Detroit, MI, USA
Conf. Sponsor: Wayne State Univ.; IEEE Circuits & Syst.
Soc
Treatment: Practical; Theoretical/Mathematical
Abstract: The computational cost of 3-D LCR package modeling is
reduced by several techniques. Capacitance extraction uses a novel
potential-adapted grid and an iterative equation solver. Inductance
calculation is based on a mixed analytical/numerical integration
method and a geometry dependent filament approximation. The resulting
circuit model automatically takes into account only significant LC
couplings. (8 Refs.)
Classification: B0170J (Product packaging); B2570 (Semiconductor
integrated circuits); B0290F (Interpolation and function
approximation); B1130B (Computer-aided circuit analysis and design);
C7410D (Electronic engineering computing); C4130 (Interpolation and
function approximation)
Thesaurus: Circuit analysis computing; Computational complexity;
Crosstalk; Integrated circuit interconnections; Integrated circuit
packaging; Iterative methods; VLSI
Free Terms: Three-dimensional LCR extraction; VLSI packages;
Computational cost; Capacitance extraction; Potential-adapted grid;
Iterative equation solver; Inductance calculation; Mixed
analytical/numerical integration method; Geometry dependent filament
approximation; Circuit model; LC couplings; Circuit simulation;
Crosstalk; Multiconductor systems
Item Availability: CD-ROM.
INSPEC 4838656 B9501-4180-014 C9501-5270-012
Doc Type: Journal Paper
Title: Optoelectronic integrated systems based on free-space
interconnects with an arbitrary degree of space variance
Authors: Drabik, T.J.
Affiliation: Microelectron. Res. Center, Georgia Inst. of Technol.,
Atlanta, GA, USA
Journal: Proceedings of the IEEE
Vol: 82 Iss: 11 p. 1595-622
Date: Nov. 1994
Country of Publication: USA
ISSN: 0018-9219 CODEN: IEEPAD
CCC: 0018-9219/94/$04.00
Language: English
Treatment: Theoretical/Mathematical; Experimental
Abstract: It is appealing to contemplate how VLSI or wafer-scale
integrated systems incorporating free-space optical interconnection
might outperform purely electrically interconnected systems. This
paper first provides a uniform treatment of a general class of
optical interconnects based on a Fourier-plane imaging system with an
array of sources in the object plane and an array of receptors in the
image plane. Sources correspond to data outputs of processing
'cells,' and receptors to their data inputs. A general abstract
optical imaging model, capable of representing a large class of real
systems, is analyzed to yield constructive upper bounds on system
volume that are comparable to those arising from '3-D VLSI'
computational models. These bounds, coupled with technologically
derived constraints, form the heart of a design methodology for
optoelectronic systems that uses electronic and optical elements each
to their greatest advantage, and exploits the available spatial
volume and power in the most efficient way. Many of these concepts
are embodied in a demonstration project that seeks to implement a
bit-serial, multiprocessing system with a radix-2 butterfly topology,
and incorporates various new technology developments. (130 Refs.)
Classification: B4180 (Optical logic devices and optical computing
techniques); B2550F (Metallisation and interconnection technology);
B4270 (Integrated optoelectronics); B0170J (Product packaging); C5270
(Optical computing techniques); C4230M (Multiprocessor
interconnection); C5220P (Parallel architecture); C5440
(Multiprocessing systems)
Thesaurus: Hypercube networks; Integrated circuit packaging; Integrated
optoelectronics; Interconnected systems; Optical computing; Optical
interconnections; VLSI
Free Terms: Optoelectronic integrated systems; Free-space
interconnects; Space variance; VLSI; Wafer-scale integrated systems;
Free-space optical interconnection; Fourier-plane imaging system;
Object plane; Image plane; Data outputs; Data inputs; Abstract
optical imaging model; Real systems; Constructive upper bounds;
Design methodology; Optoelectronic systems; Optical elements; Spatial
volume; Bit-serial multiprocessing system; Radix-2; Butterfly
topology
Item Availability: CD-ROM.
INSPEC 4828921 B9501-2250-004
Doc Type: Conference Paper
Title: Enhanced MCM-C package performance by formation of
improved 3-D interconnections
Authors: Sarfaraz, M.A.; Tong, C.; Yau, Y.-W.
Affiliation: IBM Corp., Hopewell Junction, NY, USA
Conf. Title: 1993 Proceedings. 43rd Electronic Components and
Technology Conference (Cat. No.93CH3205-2)
p. 1067-71
Publisher: IEEE
New York, NY, USA
Date: 1993 xvii+1166 pp.
Country of Publication: USA
ISBN: 0 7803 0794 1
CCC: 0569-5503/93/0000-1067$03.00
Language: English
Conf. Date: 1-4 June 1993
Conf. Loc: Orlando, FL, USA
Treatment: Practical; Experimental
Abstract: The authors introduce an improved 3-D interconnection
fabricating technology which uses an electron beam to generate
surface trenches in green ceramic sheets for the interconnection
wirings. The electron beam is capable of generating narrow lines as
well as high-density wiring patterns. Electron-beam-formed line
cross-sections (line width and thickness) can be adjusted for
electrical performance optimization. CMOS and ECL (emitter coupled
logic) drivers require different optimized transmission line
characteristics for high-performance digital systems. It is shown how
the interconnection's cross-sectional dimensions can be controlled by
electron-beam machining. Computer simulation results on the range of
electrical characteristics achievable in these interconnects as the
line space and line cross-section are varied are shown. (10 Refs.)
Classification: B2250 (Multichip modules); B0170J (Product packaging);
B2220G (Thick film circuits)
Thesaurus: Electron beam machining; Integrated circuit
interconnections; Multichip modules; Thick film circuits
Free Terms: MCM-C package performance; 3D interconnection fabrication
technology; Electron-beam machining; Surface trenches; Green ceramic
sheets; Interconnection wirings; High-density wiring patterns;
Electrical performance optimization; CMOS drivers; ECL drivers;
Optimized transmission line characteristics; High-performance digital
systems; Interconnection cross-sectional dimensions; Computer
simulation; Line width
Item Availability: CD-ROM.
INSPEC 4828908 B9501-0170J-008 C9501-5490-002
Doc Type: Conference Paper
Title: SS-1 supercomputer cooling system
Authors: Ing, P.; Sperry, C.; Philstrom, R.; Claybaker, P.;
Webster, J.; Cree, R.
Conf. Title: 1993 Proceedings. 43rd Electronic Components and
Technology Conference (Cat. No.93CH3205-2)
p. 218-37
Publisher: IEEE
New York, NY, USA
Date: 1993 xvii+1166 pp.
Country of Publication: USA
ISBN: 0 7803 0794 1
CCC: 0569-5503/93/0000-0218$3.00
Language: English
Conf. Date: 1-4 June 1993
Conf. Loc: Orlando, FL, USA
Treatment: Application; Practical
Abstract: To achieve the speeds required of the SS-1 supercomputer,
a high power ECL chip set was developed for the CPU. The 0.65 cm/sup
2/ chip has an absolute maximum power of 40 watts, translating to a
chip level heat flux of 95 W/cm/sup 2/. To achieve minimum signal
line length, a compact 3D packaging configuration is required. Board
pitch in a 3D module is 2.1 cm for the double-sided CPU and 1.96 cm
for the double-sided memory. The corresponding board level heat flux
is 15.4 W/cm/sup 2/ and the 3D power density is 3.24 W/cm/sup 3/. The
SS-1 mainframe dissipates 61 KW with an additional 11.5 KW dissipated
in the I/O concentrator. Heat must be removed at a high enough rate
to maintain chip temperatures at 65 degrees C average and 82 degrees
C maximum to ensure reliability and functionality. This paper
describes how SSI meet this challenge by a novel liquid impingement
cooling methodology. (6 Refs.)
Classification: B0170J (Product packaging); B8560 (Refrigeration and
cold storage); C5490 (Other aspects of analogue and digital
computers); C5420 (Mainframes and minicomputers)
Thesaurus: Cooling; Mainframes; Multichip modules; Packaging;
Refrigeration
Free Terms: SS-1 supercomputer; Cooling system; High power ECL chip
set; Chip level heat flux; Minimum signal line length; 3D packaging
configuration; Board pitch; Double-sided CPU; 3D power density; SS-1
mainframe; I/O concentrator; Chip temperatures; Liquid impingement
cooling; 40 W; 2.1 Cm; 1.96 Cm; 61 KW; 11.5 KW; 65 DegC; 82 DegC
Numerical Index: Power 4.0E+01 W; Size 2.1E-02 m; Size 1.96E-02 m;
Power 6.1E+04 W; Power 1.15E+04 W; Temperature 3.38E+02 K;
Temperature 3.55E+02 K
Item Availability: CD-ROM.
INSPEC 4828907 B9501-0170J-007
Doc Type: Conference Paper
Title: Accelerated life test of z-axis conductive adhesives
Authors: Chang, D.D.; Fulton, J.A.; Ling, H.C.; Schmidt, M.B.;
Sinitski, R.E.; Wong, C.P.
Affiliation: Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA
Conf. Title: 1993 Proceedings. 43rd Electronic Components and
Technology Conference (Cat. No.93CH3205-2)
p. 211-17
Publisher: IEEE
New York, NY, USA
Date: 1993 xvii+1166 pp.
Country of Publication: USA
ISBN: 0 7803 0794 1
CCC: 0569-5503/93/0000-0211$3.00
Language: English
Conf. Date: 1-4 June 1993
Conf. Loc: Orlando, FL, USA
Treatment: Application; Practical; Experimental
Abstract: Conductive-particles filled adhesives have been widely
used for flex-to-rigid board interconnections in many consumer
electronics applications, such as calculators and palmcorders. Most
of the applications were in coarse pitch interconnections where the
adjacent conductor's distance is greater than 10 mil. The success of
coarse pitch applications has increased the interest to use such
adhesives in fine pitch applications, such as flip-chip on board
interconnection. Since these materials contain metallic particles to
conduct currents in the z-direction (i.e. perpendicular to the plane
of circuit board), their propensity for metal migration is a concern.
Therefore we have applied accelerated temperature, humidity and bias
(THB) tests to a group of materials designed for fine pitch
applications. Our studies include two phases. Phase-I focused on the
high voltage (100 V) THB test and the associated conduction and
failure mechanisms. Phase-II evaluates the time-to-fail under medium
(50 V) and low voltage (10 V) THB conditions. The results of Phase-I
studies showed significant metal migration in our tests, and we
proposed enhanced electric field stresses (10/sup 4/ to 10/sup 5/
V/cm) as the driving force for failures. (6 Refs.)
Classification: B0170J (Product packaging); B0170E (Production
facilities and engineering); B2240 (Microassembly techniques); B0170N
(Reliability); B0550 (Composite materials (engineering materials
science))
Thesaurus: Adhesion; Consumer electronics; Failure analysis; Fine-pitch
technology; Flexible structures; Flip-chip devices; Integrated
circuit packaging; Life testing; Particle reinforced composites
Free Terms: Accelerated life test; Z-axis conductive adhesives;
Conductive-particles filled adhesives; Consumer electronics; Fine
pitch applications; Flip-chip on board interconnection; Metal
migration; Failure mechanisms; Time-to-fail evaluation; Electric
field stresses; 10 To 100 V
Numerical Index: Voltage 1.0E+01 to 1.0E+02 V
Item Availability: CD-ROM.
INSPEC 4823770 B9412-0170J-123 C9412-5490-009
Doc Type: Conference Paper
Title: Spray cooling for the 3-D cube computer
Authors: Tilton, D.E.; Tilton, C.L.; Moore, C.J.; Ackerman, R.E.
Affiliation: Isothermal Syst. Res. Inc., Colton, WA, USA
Conf. Title: InterSociety Conference on Thermal Phenomena in
Electronic Systems. I-THERM IV. THEME: 'Concurrent
Engineering and Thermal Phenomena' (Cat. No.94CH3340-7)
p. 169-76
Publisher: IEEE
New York, NY, USA
Date: 1994 xi+292 pp.
Country of Publication: USA
ISBN: 0 7803 1372 0
CCC: 0 7803 1372 0/94/$3.00
Language: English
Conf. Date: 4-7 May 1994
Conf. Loc: Washington, DC, USA
Conf. Sponsor: K-16 on Heat Transfer in Electron.
Equipment, Heat Transfer Div., ASME; Electron.
Packaging Div. ASME; Components, Packaging &
Manuf. Technol. IEEE; Int. Soc. Hybrid
Microelectron.; NIST
Treatment: Application; Practical; Experimental
Abstract: The results of an experimental investigation into high
performance thermal management for an advanced 3-D computer are
presented. Chips are mounted on synthetic diamond substrates. The
substrates are then stacked and integrated with vertical vias. Two
faces of the resulting 'cube' computer are reserved for clamping the
structure together, two are reserved for power insertion and signal
I/O, and the remaining two faces are spray cooled. The heat generated
by the chips is conducted laterally out to the cube faces in the high
thermal conductivity diamond substrates. The edges of the substrates
protrude through a seal plate into a compact spray chamber. Miniature
atomizers are used to spray a dielectric coolant onto the substrate
edges where the coolant vaporizes to carry away the waste heat. The
vapor is condensed in an ambient heat exchanger and the liquid is
recycled in a closed-loop system. Experimental results are presented
for two different spray plate configurations using a stack of copper
heater plates to simulate one half of the computer. Finite element
analysis is used to aid in interpretation of the results and predict
the junction temperatures that would result from a given spray plate
configuration, computer geometry, and chip power loading. The results
indicate that very high volume density heat removal is possible
(15-20 kW from a four inch cube). Thus, the 3-D computer concept may
be suitable for very high performance computing. (2 Refs.)
Classification: B0170J (Product packaging); B0290T (Finite element
analysis); C5490 (Other aspects of analogue and digital computers);
C4185 (Finite element analysis); C5440 (Multiprocessing systems)
Thesaurus: Cooling; Finite element analysis; Packaging
Free Terms: Spray cooling; 3D cube computer; Thermal management;
Synthetic diamond substrates; Vertical vias; Compact spray chamber;
Dielectric coolant; Ambient heat exchanger; Closed-loop system;
Copper heater plates; Finite element analysis; Junction temperatures;
Computer geometry; Chip power loading; Heat removal; 15 To 20 kW; 4
In
Numerical Index: Power 1.5E+04 to 2.0E+04 W; Size 1.0E-01 m
Item Availability: CD-ROM.
INSPEC 4823761 B9412-0170J-117
Doc Type: Conference Paper
Title: Modelling of thermal vias in thin film multichip modules
Authors: Christiaens, F.; Beyne, E.; Berghmans, J.
Affiliation: IMEC, Heverlee, Belgium
Conf. Title: InterSociety Conference on Thermal Phenomena in
Electronic Systems. I-THERM IV. THEME: 'Concurrent
Engineering and Thermal Phenomena' (Cat. No.94CH3340-7)
p. 101-7
Publisher: IEEE
New York, NY, USA
Date: 1994 xi+292 pp.
Country of Publication: USA
ISBN: 0 7803 1372 0
CCC: 0 7803 1372 0/94/$3.00
Language: English
Conf. Date: 4-7 May 1994
Conf. Loc: Washington, DC, USA
Conf. Sponsor: K-16 on Heat Transfer in Electron.
Equipment, Heat Transfer Div., ASME; Electron.
Packaging Div. ASME; Components, Packaging &
Manuf. Technol. IEEE; Int. Soc. Hybrid
Microelectron.; NIST
Treatment: Theoretical/Mathematical
Abstract: A semi-analytical model is presented for evaluating the
thermal resistance of via networks used in thin film multichip
modules. Correlations between dimensionless groups were derived from
numerical data. Therefore, the via network was divided in three basic
elements. This allows one to reconstruct the network as a series and
parallel connection. The results of this semi-analytical model are
compared with those of an existing analytical model and a 3D finite
element model. Good agreement between the three models was obtained.
The heat conduction efficiency of a staggered thermal via network is
defined and the influence of several parameters was investigated.
(6 Refs.)
Classification: B0170J (Product packaging); B2220E (Thin film circuits)
Thesaurus: Modelling; Multichip modules; Thermal analysis; Thermal
resistance; Thin film circuits
Free Terms: Thermal vias; Thin film multichip modules; Semi-analytical
model; Thermal resistance; Via networks; Heat conduction efficiency;
Staggered thermal via network; MCM; Modelling
Item Availability: CD-ROM.
INSPEC 4823756 B9412-2210B-018
Doc Type: Conference Paper
Title: Thermal design rules for electronic components on
conducting boards in passively cooled enclosures
Authors: Lall, B.S.; Ortega, A.; Kabir, H.
Affiliation: Dept. of Aerosp. & Mech. Eng., Arizona Univ., Tucson, AZ,
USA
Conf. Title: InterSociety Conference on Thermal Phenomena in
Electronic Systems. I-THERM IV. THEME: 'Concurrent
Engineering and Thermal Phenomena' (Cat. No.94CH3340-7)
p. 50-61
Publisher: IEEE
New York, NY, USA
Date: 1994 xi+292 pp.
Country of Publication: USA
ISBN: 0 7803 1372 0
CCC: 0 7803 1372 0/94/$3.00
Language: English
Conf. Date: 4-7 May 1994
Conf. Loc: Washington, DC, USA
Conf. Sponsor: K-16 on Heat Transfer in Electron.
Equipment, Heat Transfer Div., ASME; Electron.
Packaging Div. ASME; Components, Packaging &
Manuf. Technol. IEEE; Int. Soc. Hybrid
Microelectron.; NIST
Treatment: Practical
Abstract: A better understanding is needed of the approaches and
limitations for rejecting heat dissipated from VLSI components
mounted on multi-layer printed circuit boards housed in small
enclosures, as for example those encountered in small consumer
electronics, and, in notebook, laptop, or hand-held personal
computers. This paper derives new first order thermal design formulae
for determining the peak temperatures of sources on conducting
substrates, and for determining the thermal 'zone of influence' or
'footprint' associated with a component on a board. A one-dimensional
thin board radial fin approach is used with inclusion of a circular
source to represent the heat dissipating component. Exact solutions
are presented for sources at the center, edge, and corner of a
rectangular board. The results are compared with with both 2-d and
3-d calculations for rectangular sources on a board using the finite
element method. Excellent agreement is found in predicting the
maximum temperature, with maximum differences of order 10%. Simple
algebraic design formulae, useful for rapid estimation, are derived
from the complete solutions by taking advantage of the asymptotic
behavior at small and large values of the board parameter, m. An
unambiguous thermal footprint radius is defined in terms of the
tangent line at the inflection point of the temperature profile.
Parametric studies show that the radius corresponds to the point at
which the board temperature drops to roughly 18% of its peak
temperature, for all variations of board thickness and conductivity
of practical interest. The simple analytical model is used to predict
the temperatures on a populated board, using a linear superposition
principle, and it is found to be in good agreement with experimental
results for boards with multiple heat sources. (23 Refs.)
Classification: B2210B (Printed circuit layout and design); B0290T
(Finite element analysis); B0170J (Product packaging)
Thesaurus: Cooling; Finite element analysis; Packaging; Printed circuit
design
Free Terms: Thermal design rules; Electronic components; Conducting
boards; Passively cooled enclosures; VLSI components; Multi-layer
printed circuit boards; One-dimensional thin board radial fin;
Rectangular board; Finite element method; Maximum temperature;
Asymptotic behavior; Thermal footprint radius; Board temperature;
Linear superposition principle
Item Availability: CD-ROM.
INSPEC 4823455 B9412-0170J-077
Doc Type: Conference Paper
Title: High-frequency inductance measurements and
characterization of alloy 42 and copper packages
Authors: Chi-Taou Tsai; Osorio, R.; Wai-Yeung Yip; Sparkman, A.;
Sharma, R.; Astrain, H.
Affiliation: Motorola Inc., Chandler, AZ, USA
Conf. Title: 1993 Proceedings. 43rd Electronic Components and
Technology Conference (Cat. No.93CH3205-2)
p. 635-40
Publisher: IEEE
New York, NY, USA
Date: 1993 xvii+1166 pp.
Country of Publication: USA
ISBN: 0 7803 0794 1
CCC: 0569-5503/93/0000-0635$3.00
Language: English
Conf. Date: 1-4 June 1993
Conf. Loc: Orlando, FL, USA
Treatment: Theoretical/Mathematical; Experimental
Abstract: A network analysis based high-frequency inductance
technique was used to measure the package inductance of various A42
and Cu QFP packages. A continuous frequency range of 2.6 MHz to >500
MHz corresponding to the relevant speed/bandwidth of today's ICs was
employed. Results indicated that while the inductance of all the Cu
packages were essentially constant across the frequency band, the
inductance of A42 packages varied appreciably with the frequency. The
inductance of a typical A42 package was three times that of a Cu
package at 2.6 MHz but decreased to only 10%-20% higher than that of
a Cu package above 250 MHz. The lead resistance of A42 also increased
sharply with increasing frequency and could become an important
factor in determining the electrical performance. Based upon the
preliminary analyses, the frequency-dependent inductance and
resistance of A42 packages were attributed to the interaction between
the skin effect and the non-unity permeability of ferromagnetic
materials. To verify the theory and to test possible electrical
enhancement for the A42, different surface-treated packages,
including an Au-plated A42, a Pd/Ni-plated A42 and a Pd/Ni-plated Cu
CQFP packages were characterized for their inductance and resistance.
A 3-D field solver was also used to derive the permeability of the
A42 materials at different frequencies. To further study the impact
on high-speed digital chips where signals are usually analyzed in the
time domain, a test structure made of both A42 traces and Cu traces
was characterized using a time domain reflectometer for impedance,
delay, and crosstalk. Both the frequency-domain and the time-domain
results for A42 and Cu packages are summarized in this paper and
their implications discussed. (5 Refs.)
Classification: B0170J (Product packaging); B7310J (Impedance and
admittance measurement)
Thesaurus: Copper; Crosstalk; Delays; Inductance; Inductance
measurement; Iron alloys; Magnetic permeability; Packaging; Skin
effect; Time-domain analysis
Free Terms: High-frequency inductance technique; HF inductance
measurements; Characterization; Alloy 42 packages; Cu packages;
Network analysis; QFP packages; IC packages; Lead resistance; Skin
effect; Nonunity permeability; Ferromagnetic materials;
Surface-treated packages; Au-plated A42; Pd/Ni-plated A42;
Pd/Ni-plated Cu; 3D field solver; High-speed digital chips; Time
domain analysis; Crosstalk; Delay; 2.6 To 500 MHz; PdNi-Cu
Numerical Index: Frequency 2.6E+06 to 5.0E+08 Hz
Chemical Index: PdNi-Cu/int PdNi/int Cu/int Ni/int Pd/int PdNi/bin
Ni/bin Pd/bin Cu/el; PdNi/int Fe/int Ni/int Pd/int PdNi/bin Fe/bin
Ni/bin Pd/bin
Item Availability: CD-ROM.
INSPEC 4823454 B9412-0170J-076