1. W. Marwood and A. Beaumont-Smith. The architecture and optimisation of systolic ring processors for matrix computations. CHiPTec Tech. Rep. GaAs-92-05, The University of Adelaide, March 1992.



2. A. Beaumont-Smith, W. Marwood, C.C. Lim, and K. Eshraghian. Ultra high speed gallium arsenide systems: design methodology, CAD tools and architectures. CHiPTec Tech. Rep. GaAs-91-01, The University of Adelaide, March 1991.



3. W. Marwood. A generalized systolic array serial floating point adder and accumulator. CHiPTec Tech. Rep. GaAs-91-21, The University of Adelaide, July 1991.



4. W. Marwood. A generalized systolic ring serial floating point multiplier. CHiPTec Tech. Rep. GaAs-91-20, The University of Adelaide, July 1991.



5. W. Marwood. A number theory mapping generator for addressing matrix structures. CHiPTec Tech. Rep. GaAs-91-19, The University of Adelaide, July 1991.



6. W. Marwood. A generialised systolic ring serial floating point multipler. CHiPTec Tech. Rep. GaAs-90-14, The University of Adelaide, June 1990.



7. W. Marwood. The maximum computation rate of systolic array processors. CHiPTec Tech. Rep. GaAs-90-01, The University of Adelaide, January 1990.



8. W. Marwood. An address generator for a marix product machine. CHiPTec Tech. Rep. GaAs-89-03, The University of Adelaide, August 1989.



9. W. Marwood. The implementation of the discrete fourier transform on a matrix co-processor (SCAP). CHiPTec Tech. Rep. GaAs-89-08, The University of Adelaide, 1989.



10. W. Marwood. The implementation of the discrete fourier transform on a systolic configurable array processor. CHiPTec Tech. Rep. GaAs-89-01, The University of Adelaide, June 1989.



11. W. Marwood. The impossible dream: faster systems from slower elements. CHiPTec Tech. Rep. GaAs-89-07, The University of Adelaide, 1989.



12. W. Marwood and K. Eshraghian. VLSI systolic processors - an architecture for GaAs. CHiPTec Tech. Rep. GaAs-89-04, The University of Adelaide, October 1989.

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