1. B. J. Phillips. Elliptic Curve Cryptography Over Prime Finite Fields: A Short Primer. CHiPTec Tech. Rep. CHIPTEC-08-01, The University of Adelaide, January 2008.

1. Z. Lim and B. J. Phillips. An RNS-Enabled Architecture on the Tensilica Xtensa LX Processor. CHiPTec Tech. Rep. CHIPTEC-07-01, The University of Adelaide, April 2007. Note: Attachments: https://www.eleceng.adelaide.edu.au/students/undergrad/courses/4037/CHiPTecLibrary/CHIPTEC-07-01_Attachments.zip.

1. T. Diakiw. VHDL Coding Guide for a Public Key Crypto Chip. CHiPTec Tech. Rep. CHIPTEC-05-05, The University of Adelaide, October 2005.



2. D. Kelly. Research proposal: arithmetic data value speculation. CHiPTec Tech. Rep. CHIPTEC-05-03, The University of Adelaide, September 2005.



3. Y. Kong and B. J. Phillips. A Montgomery modular multiplier for RNS channel operations. CHiPTec Tech. Rep. CHIPTEC-05-01, The University of Adelaide, November 2005.



4. Y. Kong and B. J. Phillips. A classical modular multiplier for RNS channel operations. CHiPTec Tech. Rep. CHIPTEC-05-02, The University of Adelaide, November 2005.



5. B. J. Phillips and J. P. Rosser. Radix 2 Quotient Digit Selection Function for a Public Key Crypto Chip. CHiPTec Tech. Rep. CHIPTEC-05-06, The University of Adelaide, July 2005.



6. J. Rosser, T. Diakiw, and S. Thakur. Public Key Crypto Chip. CHiPTec Tech. Rep. CHIPTEC-05-04, The University of Adelaide, October 2005.



7. E. Watts and B. J. Phillips. Extending the 2005 CryptoChip. CHiPTec Tech. Rep. CHIPTEC-05-07, The University of Adelaide, November 2005.

1. Andrew Beaumont-Smith. MatRISC-1 Architecture Study and Design. CHiPTec Tech. Rep. CHIPTEC-99-02, The University of Adelaide, April 1999.

1. Sam S. Appleton. Test Board Setup for the ECSTAC Microprocessor Device. CHiPTec Tech. Rep. HPCA-ECS-97-01, The University of Adelaide, January 1997.



2. Andrew Beaumont-Smith. IP Organisation and Instruction Set Architecture for the MDMA. CHiPTec Tech. Rep. CHIPTEC-97-04, The University of Adelaide, February 1997.



3. Andrew Beaumont-Smith. MDMA Analysis. CHiPTec Tech. Rep. CHIPTEC-97-03, The University of Adelaide, February 1997.



4. Andrew Beaumont-Smith. Proposal for Research. CHiPTec Tech. Rep. CHIPTEC-97-05, The University of Adelaide, February 1997.



5. Andrew Beaumont-Smith. The Development of a MATRISC Processor. CHiPTec Tech. Rep. CHIPTEC-97-02, The University of Adelaide, February 1997.



6. Andrew Beaumont-Smith and Kiet To. Multi-Dimensional Memory Array on a Two Dimensional Processing Element Array. CHiPTec Tech. Rep. CHIPTEC-97-01, The University of Adelaide, January 1997.



7. Stephane Lefrere. Arithmetic Unit Designs for the MatRISC Processor. CHiPTec Tech. Rep. CHIPTEC-97-06, The University of Adelaide, September 1997.

1. Said F. Al-Sarawi and Derek Abbott. Review of 3D VLSI Packaging Technology. CHiPTec Tech. Rep. CHIPTEC-96-02, The University of Adelaide, December 1996.



2. Sam Appleton. Asynchronous Pipeline Design using GaAs PDLL Logic and new CMOS dynamic techniques. CHiPTec Tech. Rep. HPCA-ECS-96-04, The University of Adelaide, October 1996.



3. Sam Appleton. Implementation of Instruction and Data Caches for the ECSTAC Microprocessor. CHiPTec Tech. Rep. HPCA-ECS-96-02, The University of Adelaide, June 1996.



4. Andrew Beaumont-Smith and Neil Burgess. Sub-nanosecond GaAs 32-bit Adder. CHiPTec Tech. Rep. CHIPTEC-96-01, The University of Adelaide, October 1996.



5. Nicholas Betts. Design and Simulation of the MatRISC Load/Store Architecture. CHiPTec Tech. Rep. HPCA-MAT-96-03, The University of Adelaide, June 1996.



6. Nicholas Betts. Inverted Address Generation for a Matrix Processor. CHiPTec Tech. Rep. HPCA-MAT-96-01, The University of Adelaide, June 1996.



7. Nicholas Betts. Multiplication on the Load/Store Architecture. CHiPTec Tech. Rep. HPCA-MAT-96-02, The University of Adelaide, June 1996.



8. Michael Liebelt. A Proposal for Research on the Testability of Asynchronous Circuits. CHiPTec Tech. Rep. HPCA-ECS-96-01, The University of Adelaide, June 1996.



9. Michael Liebelt and Neil Burgess. The Effects of Exitory Faults in Semi-modular Asynchronous Circuits. CHiPTec Tech. Rep. HPCA-ECS-96-03, The University of Adelaide, July 1996.

1. Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. Instruction and Data Caches for the ECSTAC-P Microprocessor. CHiPTec Tech. Rep. HPCA-ECS-95-04, The University of Adelaide, February 1995.



2. Michael Liebelt. Progress Report on Research on the Testing of Asynchronous Circuits. CHiPTec Tech. Rep. HPCA-ECS-95-03, The University of Adelaide, 1995.



3. A. Moini, A. Bouzerdoum, and K. Eshraghian. Statistical Analysis of the Accuracy of Current-Mirror Structure. CHiPTec Tech. Rep. GaAs-95-01, The University of Adelaide, March 1995.



4. Shannon V. Morton. SIGMA: Single Instruction-type General Machine Architecture. CHiPTec Tech. Rep. HPCA-ECS-95-05, The University of Adelaide, February 1995.



5. Shannon V. Morton and Sam S. Appleton. Deadlock and Persistency Detection of Temporal Specifications. CHiPTec Tech. Rep. HPCA-ECS-95-02, The University of Adelaide, January 1995.



6. B. J. Phillips and N. Burgess. An Overview Of Public Key Cryptography. CHiPTec Tech. Rep. DAG-MOD-01, The University of Adelaide, October 1995.

1. Sam S. Appleton, Shannon V. Morton, Andrew B. Johnson, and Michael J. Liebelt. ECSTACBus: External Bus Protocol for the ECSTAC Microprocessor. CHiPTec Tech. Rep. HPCA-ECS-94-03, The University of Adelaide, 1994.



2. Sam S. Appleton, Shannon V. Morton, Andrew B. Johnson, and Michael J. Liebelt. Instruction Set Architecture of ECSTAC-P. CHiPTec Tech. Rep. HPCA-ECS-94-01, The University of Adelaide, 1994.



3. Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. Instruction and Data Caches for the ECSTAC Microprocessor. CHiPTec Tech. Rep. HPCA-ECS-94-07, The University of Adelaide, 1994.



4. Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. Metastability in ECS Systems. CHiPTec Tech. Rep. HPCA-ECS-94-18, The University of Adelaide, 1994.



5. Nicholas M. Betts. Code Document: 0: The Hewitt NURBS Package and Data Structure. CHiPTec Tech. Rep. HPCA-SME-94-02, The University of Adelaide, September 1994.



6. Nicholas M. Betts. Code Document: 1 NURBS Evaluation and Derivatives. CHiPTec Tech. Rep. HPCA-SME-94-03, The University of Adelaide, December 1994.



7. Nicholas M. Betts. Code Document: la Polynomial Evaluation. CHiPTec Tech. Rep. HPCA-SME-94-14, The University of Adelaide, December 1994.



8. Nicholas M. Betts. Research Proposal: Hardware Acceleration of Solid Modelling with Free Form Curves and Surfaces. CHiPTec Tech. Rep. HPCA-SME-94-01, The University of Adelaide, June 1994.



9. Nicholas M. Betts. Strategies for Hardware Evaluation of NURBS. CHiPTec Tech. Rep. HPCA-SME-95-01, The University of Adelaide, November 1994.



10. S. Cui, M. J. Liebelt, K. Eshraghian, and N. Burgess. A Modified Ring Notation Approach for Implementation of a GaAs Core Processor for a Solid Modelling Accelerator. CHiPTec Tech. Rep. GaAs-94-02, The University of Adelaide, 1994.



11. A. R. Moini. Bug-Eye II The Second Generation of a Motion Detection Chip. CHiPTec Tech. Rep. GaAs-94-03, The University of Adelaide, September 1994.



12. Shannon V. Morton, Sam S. Appleton, and Michael J. Liebelt. 24 Bit Adder, Comparator and Stack Access Stages for ECSTAC-P. CHiPTec Tech. Rep. HPCA-ECS-94-05, The University of Adelaide, 1994.



13. Shannon V. Morton, Sam S. Appleton, and Michael J. Liebelt. Instruction Decode and Operand Fetch Process for ECSTAC-P. CHiPTec Tech. Rep. HPCA-ECS-94-02, The University of Adelaide, 1994.



14. Shannon V. Morton, Sam S. Appleton, and Michael J. Liebelt. Interface to the Execution Units and the ALU and PC Structures for ECSTAC-P. CHiPTec Tech. Rep. HPCA-ECS-94-06, The University of Adelaide, 1994.



15. Shannon V. Morton, Sam S. Appleton, and Michael J. Liebelt. Register Control, Tags and Write Back Strategies for ECSTAC-P. CHiPTec Tech. Rep. HPCA-ECS-94-04, The University of Adelaide, 1994.



16. Tim Shaw and Michael Liebelt. A Reliable Microprocessor Control Systems with Multiple Redundancy. CHiPTec Tech. Rep. HPCA-CRC-94-12, The University of Adelaide, 1994.

1. Sam S. Appleton and Shannon V. Morton. A Pipelined ECS Cache Design. CHiPTec Tech. Rep. HPCA-ECS-93-17, The University of Adelaide, December 1993.



2. Sam S. Appleton and Shannon V. Morton. Implementation of an ECS SRAM. CHiPTec Tech. Rep. HPCA-ECS-93-15, The University of Adelaide, November 1993.



3. Sam S. Appleton and Shannon V. Morton. Petri Nets applied to the ECS Methodology. CHiPTec Tech. Rep. HPCA-ECS-93-14, The University of Adelaide, November 1993.



4. Sam S. Appleton, Shannon V. Morton, M. J. Liebelt, and D. A. Pucknell. Design of a controller for an event controlled cache system. CHiPTec Tech. Rep. HPCA-ECS-93-07, The University of Adelaide, June 1993.



5. S. Cui, M. J. Liebelt, and K. Eshraghian. Using unified technology to implement a solid modelling accelerator: project report I. CHiPTec Tech. Rep. GaAs-93-09, The University of Adelaide, July 1993.



6. K. Eshraghian and E. Chu. Architectural overview of switches suiyable for implementing ATM switch nodes. CHiPTec Tech. Rep. GaAs-93-06, The University of Adelaide, March 1993.



7. K. Eshraghian, M. K. McGeever, E. Chu, J. Jakobsen, and M.J. Liebelt. Implementation of an 8x8 B-ISDN ATM switch in gallium arsenide. CHiPTec Tech. Rep. GaAs-93-08b, The University of Adelaide, July 1993.



8. K. Eshraghian and A. R. Moini. Interfacing and bus structure in GaAs design. CHiPTec Tech. Rep. GaAs-93-07a, The University of Adelaide, April 1993.



9. K. Eshraghian and A. R. Moini. Packaging for very high speed VLSI. CHiPTec Tech. Rep. GaAs-93-04, The University of Adelaide, March 1993.



10. A. B. Johnson. A comparison of language features suitablae for use in a formal, operational, temporal specification of digital circuits. CHiPTec Tech. Rep. HPCA-ECS-93-19a, The University of Adelaide, 1993.



11. P. Lascala and D. Quarisa. 56 bit parallel to serial converter, 56 bit serial to parallel converter, 56 bit counter. CHiPTec Tech. Rep. GaAs-93-08a, The University of Adelaide, October 1993.



12. Shannon V. Morton. A reconfigurable ECS Multi-module FFT. CHiPTec Tech. Rep. HPCA-ECS-93-08, The University of Adelaide, August 1993.



13. Shannon V. Morton. An ECS SRAM Design. CHiPTec Tech. Rep. HPCA-ECS-93-06, The University of Adelaide, June 1993.



14. Shannon V. Morton. Computational Cells of the ALU V.2. CHiPTec Tech. Rep. HPCA-ECS-93-04, The University of Adelaide, February 1 1993.



15. Shannon V. Morton. Computational Cells of the ALU V.l. CHiPTec Tech. Rep. HPCA-ECS-93-03, The University of Adelaide, January 1993.



16. Shannon V. Morton. Event Control of the ALU. CHiPTec Tech. Rep. HPCA-ECS-93-02, The University of Adelaide, January 1993.



17. Shannon V. Morton. Pipelining Principles. CHiPTec Tech. Rep. HPCA-ECS-93-01, The University of Adelaide, January 1993.



18. Shannon V. Morton and Sam S. Appleton. ECS Compilation Techniques - Translation of Linear Code into Temporal Specifications. CHiPTec Tech. Rep. HPCA-ECS-93-18, The University of Adelaide, December 1993.



19. Shannon V. Morton and Sam S. Appleton. ECS Compilation Techniques - Translation of Program Constructs into Temporal Specifications. CHiPTec Tech. Rep. HPCA-ECS-93-16, The University of Adelaide, November 1993.



20. Shannon V. Morton and Sam S. Appleton. Event Controlled Systems - Techniques and Concepts. CHiPTec Tech. Rep. HPCA-ECS-93-05, The University of Adelaide, May 1993.



21. Shannon V. Morton and Sam S. Appleton. Event Controlled Systems Design Methodology using a Temporal Specification Approach. CHiPTec Tech. Rep. HPCA-ECS-93-10, The University of Adelaide, September 1993.



22. Shannon V. Morton and Sam S. Appleton. Temporal Transition Graphs for Event Controlled Systems. CHiPTec Tech. Rep. HPCA-ECS-93-12, The University of Adelaide, October 1993.



23. Shannon V. Morton and Sam S. Appleton. The Design of a QR42 Interface using the ECS Methodology. CHiPTec Tech. Rep. HPCA-ECS-93-09, The University of Adelaide, August 1993.



24. X. T. Nguyen, R. Bogner, K. Eshraghian, D. Abbott, A. Bouzerdoum, A. Moini, and A. Yakovleff. Robotic micro-sensor based on insect vision. CHiPTec Tech. Rep. GaAs-93-05, The University of Adelaide, March 1993.



25. X. T. Nguyen, R. E. Bogner, K. Eshraghian, A. Bouzerdoum, D. Abbott, A. Moini, and A. Yakovleff. Optical interfaces for the front-end visual processing system based upon insect vision. CHiPTec Tech. Rep. GaAs-93-07b, The University of Adelaide, June 1993.



26. Nozar Tabrizi. 256 x 4 bit dynamic GaAs RAM. CHiPTec Tech. Rep. GaAs-93-22, The University of Adelaide, December 1993.



27. Nozar Tabrizi. Restoring and non-restoring logic in GaAs. CHiPTec Tech. Rep. GaAs-93-21, The University of Adelaide, December 1993.

1. A. Beaumont-Smith and K. Eshraghian. Comparison of gallium arsenide MESFET process technologies. CHiPTec Tech. Rep. GaAs-92-14, The University of Adelaide, August 1992.



2. E. Chu, S. Cui, and A. R. Moini. The pseudo-current-mode logic familt (PCML). CHiPTec Tech. Rep. GaAs-92-06, The University of Adelaide, April 1992.



3. S. Cui, E. Chu, and A. R. Moini. Source follower FET logic (SFFL). CHiPTec Tech. Rep. GaAs-92-07, The University of Adelaide, May 1992.



4. K. Eshraghian. Design methodology and layout style for very high speed circuits and subsystems. CHiPTec Tech. Rep. GaAs-92-04, The University of Adelaide, 1992.



5. K. Eshraghian. Optimisation of high speed VLSI systems: physical mapping. CHiPTec Tech. Rep. GaAs-92-03, The University of Adelaide, 1992.



6. K. Eshraghian. Technologies for future very high speed switching systems. CHiPTec Tech. Rep. GaAs-92-13, The University of Adelaide, May 1992.



7. K. Eshraghian. Very high and ultra speed VLSI technologies. CHiPTec Tech. Rep. GaAs-92-02, The University of Adelaide, 1992.



8. K. Eshraghian and D. Abbott. Imaging system for aerospace vehicle. CHiPTec Tech. Rep. GaAs-92-01, The University of Adelaide, February 1992.



9. K. Eshraghian, E. Chu, A. R. Moini, and S. Cui. Design and comparison of GaAs static logic suitable for VLSI implementation. CHiPTec Tech. Rep. GaAs-92-15, The University of Adelaide, November 1992.



10. W. Marwood and A. Beaumont-Smith. The architecture and optimisation of systolic ring processors for matrix computations. CHiPTec Tech. Rep. GaAs-92-05, The University of Adelaide, March 1992.



11. D. Solomon. Header error correction using cyclic redundancy codes. CHiPTec Tech. Rep. GaAs-92-10, The University of Adelaide, May 1992.

1. D. Abbott, S. Cui, K. Eshraghian, and E. McCabe. Photovoltaic gate biasing edge effect in GaAs MESFETs. CHiPTec Tech. Rep. GaAs-91-11, The University of Adelaide, June 1991.



2. D. Abbott and K. Eshraghian. Gallium arsenide MESFET imager. CHiPTec Tech. Rep. GaAs-91-18, The University of Adelaide, 1991.



3. A. Beaumont-Smith, W. Marwood, C.C. Lim, and K. Eshraghian. Ultra high speed gallium arsenide systems: design methodology, CAD tools and architectures. CHiPTec Tech. Rep. GaAs-91-01, The University of Adelaide, March 1991.



4. K. Eshraghian, E. Bushehri, and R. Bayford. Characterization and performance analysis of gallium arsenide MESFET structures, using a new layout apporach. CHiPTec Tech. Rep. GaAs-91-13, The University of Adelaide, July 1991.



5. K. Eshraghian, E. Bushehri, and R. Bayford. Characterization and performance estimation of MESFET structures. CHiPTec Tech. Rep. GaAs-91-12, The University of Adelaide, July 1991.



6. K. Eshraghian, R. Sarmiento, P. P. Carballo, and A. Nunez. Speed-Area-Power optimization for DCFL and SDCFL class of logic using ring notation. CHiPTec Tech. Rep. GaAs-91-10, The University of Adelaide, May 1991.



7. R. Flay. Test vector generation for combinational logic circuits. CHiPTec Tech. Rep. GaAs-91-07, The University of Adelaide, May 1991.



8. C. C. Kong. Control logic and software for a high speed tester. CHiPTec Tech. Rep. GaAs-91-06, The University of Adelaide, May 1991.



9. N. Laycock. BiCMOS VLSI layout, design rule checking, and circuit extraction. CHiPTec Tech. Rep. GaAs-91-03, The University of Adelaide, May 1991.



10. W. Marwood. A generalized systolic array serial floating point adder and accumulator. CHiPTec Tech. Rep. GaAs-91-21, The University of Adelaide, July 1991.



11. W. Marwood. A generalized systolic ring serial floating point multiplier. CHiPTec Tech. Rep. GaAs-91-20, The University of Adelaide, July 1991.



12. W. Marwood. A number theory mapping generator for addressing matrix structures. CHiPTec Tech. Rep. GaAs-91-19, The University of Adelaide, July 1991.



13. S. Mosel. Ultra high speed graphics engine architecture and polynomial evaluator in gallium arsenide. CHiPTec Tech. Rep. GaAs-91-15, The University of Adelaide, October 1991.



14. V. Nomokonov and F. Filippov. Test pattern generation for combinational logic circuits: new method and algorithm. CHiPTec Tech. Rep. GaAs-91-02, The University of Adelaide, May 1991.



15. D. Silver. 1 GHz clock generator for a GaAs IC functional tester. CHiPTec Tech. Rep. GaAs-91-04, The University of Adelaide, May 1991.



16. M. Tang. Construction of matrices of paths for graph models of combinational circuits. CHiPTec Tech. Rep. GaAs-91-08, The University of Adelaide, May 1991.



17. J. Yeung. investigation of the ability of test sets to detect physical fault in combinational logic. CHiPTec Tech. Rep. GaAs-91-05, The University of Adelaide, May 1991.



18. N. S. Yusoff. Test set derivation for combinational logic circuits using matrices of paths. CHiPTec Tech. Rep. GaAs-91-09, The University of Adelaide, May 1991.

1. Andrew Beaumont-Smith. Gallium Arsenide Network Extractor GAASNET. CHiPTec Tech. Rep. GaAs-90-05, The University of Adelaide, December 1990.



2. Andrew Beaumont-Smith. Gallium Arsenide Tutorial Exercise EGAS - NOR Gate. CHiPTec Tech. Rep. GaAs-90-03, The University of Adelaide, July 1990.



3. E. Bushehri, K. Eshraghian, and D. Abbott. Theorietical analysis of adder circuits for GaAs VLSI implementation. CHiPTec Tech. Rep. GaAs-90-02, The University of Adelaide, March 1990.



4. K. Eshraghian and D. Abbott. Progress report no. 2: imaging system for aerospace vehicle. CHiPTec Tech. Rep. GaAs-90-12, The University of Adelaide, January 1990.



5. K. Eshraghian and D. Abbott. Progress report no. 3: imaging system for aerospace vehicle. CHiPTec Tech. Rep. GaAs-90-13, The University of Adelaide, June 1990.



6. R. Long. Test head for a 1GHz gallium arsendie tester. CHiPTec Tech. Rep. GaAs-90-07, The University of Adelaide, April 1990.



7. W. Marwood. A generialised systolic ring serial floating point multipler. CHiPTec Tech. Rep. GaAs-90-14, The University of Adelaide, June 1990.



8. W. Marwood. The maximum computation rate of systolic array processors. CHiPTec Tech. Rep. GaAs-90-01, The University of Adelaide, January 1990.



9. S. Mazumdar. High speed functional tester for gallium arsenide circuits - low to high speed interface. CHiPTec Tech. Rep. GaAs-90-10, The University of Adelaide, October 1990.



10. J. McPheat. Computer interface for a 1GHz functional tester for gallium arsenide integrated circuits. CHiPTec Tech. Rep. GaAs-90-11, The University of Adelaide, October 1990.



11. D. Rogers. Functional tester for gallium arsendie integrated circuits - computer interface. CHiPTec Tech. Rep. GaAs-90-09, The University of Adelaide, April 1990.



12. A. Wakefield. High speed functional tester for gallium arsendie circuits. CHiPTec Tech. Rep. GaAs-90-08, The University of Adelaide, April 1990.

1. P. Franzon and K. Eshraghian. Achieving ULSI through defect tolerance. CHiPTec Tech. Rep. GaAs-89-06, The University of Adelaide, 1989.



2. W. Marwood. An address generator for a marix product machine. CHiPTec Tech. Rep. GaAs-89-03, The University of Adelaide, August 1989.



3. W. Marwood. The implementation of the discrete fourier transform on a matrix co-processor (SCAP). CHiPTec Tech. Rep. GaAs-89-08, The University of Adelaide, 1989.



4. W. Marwood. The implementation of the discrete fourier transform on a systolic configurable array processor. CHiPTec Tech. Rep. GaAs-89-01, The University of Adelaide, June 1989.



5. W. Marwood. The impossible dream: faster systems from slower elements. CHiPTec Tech. Rep. GaAs-89-07, The University of Adelaide, 1989.



6. W. Marwood and K. Eshraghian. VLSI systolic processors - an architecture for GaAs. CHiPTec Tech. Rep. GaAs-89-04, The University of Adelaide, October 1989.

1. K. Eshraghian and D. Abbott. Progress report no. 1: imaging system for aerospace vehicle. CHiPTec Tech. Rep. GaAs-88-01, The University of Adelaide, June 1988.

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