1. A. Beaumont-Smith and K. Eshraghian. Comparison of gallium arsenide MESFET process technologies. CHiPTec Tech. Rep. GaAs-92-14, The University of Adelaide, August 1992.



2. E. Chu, S. Cui, and A. R. Moini. The pseudo-current-mode logic familt (PCML). CHiPTec Tech. Rep. GaAs-92-06, The University of Adelaide, April 1992.



3. S. Cui, E. Chu, and A. R. Moini. Source follower FET logic (SFFL). CHiPTec Tech. Rep. GaAs-92-07, The University of Adelaide, May 1992.



4. K. Eshraghian. Design methodology and layout style for very high speed circuits and subsystems. CHiPTec Tech. Rep. GaAs-92-04, The University of Adelaide, 1992.



5. K. Eshraghian. Optimisation of high speed VLSI systems: physical mapping. CHiPTec Tech. Rep. GaAs-92-03, The University of Adelaide, 1992.



6. K. Eshraghian. Technologies for future very high speed switching systems. CHiPTec Tech. Rep. GaAs-92-13, The University of Adelaide, May 1992.



7. K. Eshraghian. Very high and ultra speed VLSI technologies. CHiPTec Tech. Rep. GaAs-92-02, The University of Adelaide, 1992.



8. K. Eshraghian and D. Abbott. Imaging system for aerospace vehicle. CHiPTec Tech. Rep. GaAs-92-01, The University of Adelaide, February 1992.



9. K. Eshraghian, E. Chu, A. R. Moini, and S. Cui. Design and comparison of GaAs static logic suitable for VLSI implementation. CHiPTec Tech. Rep. GaAs-92-15, The University of Adelaide, November 1992.



10. W. Marwood and A. Beaumont-Smith. The architecture and optimisation of systolic ring processors for matrix computations. CHiPTec Tech. Rep. GaAs-92-05, The University of Adelaide, March 1992.



11. D. Solomon. Header error correction using cyclic redundancy codes. CHiPTec Tech. Rep. GaAs-92-10, The University of Adelaide, May 1992.

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