Fault tolerant network-on-chip intrconnect:
| SPEAKER: | Mr. R. Moric |
| DATE: | Thursday, 24th May 2012 |
| TIME: | 4:10pm |
| VENUE: | 5.57 Ingkarni Wardli (Innova21) Directions |
- Abstract:
The aggressive pursuit of Moore's Law into the nanometer regime has allowed chip designers to integrate many processing cores on a single chip connected with a network on chip. However, this scaling has come at the cost of increased manufacturing process variation resulting in an increase in the number of defects and reducing manufacturing yield. This presentation will discuss a fine grained fault model and the design of a fault tolerant routing algorithm for a 2D homogenous multicore microprocessor with a network on chip and how this fault tolerant interconnect can be used to improve manufacturing yield.
- Biography:
Robert completed his Bachelor of Engineering (Computer Systems) in 2008 (Honours) at the University of Adelaide. He is currently a PhD candidate, researching fault tolerance in vlsi.
