INSPEC 5218787 B9605-5240D-017 Doc Type: Conference Paper Title: Efficient 3-D series impedance extraction using effective internal impedance Authors: Beom-Taek Lee; Tuncer, E.; Neikirk, D.P. Affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 220-2 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Theoretical/Mathematical Abstract: The effective internal impedance approach, combined with the current-filament technique, has been shown to be a very efficient way to extract frequency dependent resistance and inductance of uniform interconnects. In this study, we show that this approach can be extended to find the series impedance of three dimensional structures. A microstrip bend is studied as a simple example. (10 Refs.) Classification: B5240D (Waveguide and cavity theory) Thesaurus: Electric impedance; Microstrip discontinuities; Waveguide discontinuities Free Terms: 3D series impedance; Effective internal impedance; Current-filament technique; Frequency dependent resistance; Inductance; Interconnects; Three dimensional structures; Microstrip bend Item Availability: CD-ROM. INSPEC 5218785 B9605-0170J-044 Doc Type: Conference Paper Title: Two optimizations to accelerated method-of-moments algorithms for signal integrity analysis of complicated 3-D packages Authors: Kamon, M.; Krauter, B.; Phillips, J.; Pileggi, L.; White, J. Affiliation: Res. Lab. of Electron., MIT, Cambridge, MA, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 213-16 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Theoretical/Mathematical Abstract: In this paper we present two optimizations to accelerated Method-of-Moments algorithms. The first is an improved preconditioner for multipole-accelerated inductance extraction and the second is a set of several optimizations of the FFT-based convolution used in precorrected-FFT methods. (8 Refs.) Classification: B0170J (Product packaging); B0260 (Optimisation techniques); B0290Z (Other numerical methods) Thesaurus: Convolution; Fast Fourier transforms; Inductance; Method of moments; Optimisation; Packaging Free Terms: Optimization; Accelerated method-of-moments algorithms; Signal integrity; 3D packages; Preconditioner; Multipole method; Convolution; Precorrected FFT method; Inductance Item Availability: CD-ROM. INSPEC 5218777 B9605-1350H-013 Doc Type: Conference Paper Title: Low cost, highly integrated MMW MMIC transceiver packages Authors: Gawrouski, M.; Seashore, C.; Bosch, D.; Lamberg, J.; Loughran, S.; Rabel, J. Affiliation: Div. of Defense Syst., Alliant Techsyst., Hopkins, MN, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 183 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Practical; Experimental Abstract: Summary form only given, as follows. A producible, high density Ka-Band (35 GHz) monolithic transceiver package has been developed containing a full set of MMIC transmit/receive chips. This paper presents the results of extensive 3-D electromagnetic high frequency chip-to-chip and chip-to-microstrip line/packaging interconnect analyses. The MMIC module includes a novel chip-on-carrier design with a low cost 'Duroid' soft substrate performing the RF circuit interconnection with IF amplification. (0 Refs.) Classification: B1350H (Microwave integrated circuits); B2570 (Semiconductor integrated circuits); B0170J (Product packaging) Thesaurus: Integrated circuit design; Integrated circuit interconnections; Integrated circuit packaging; Microstrip lines; MIMIC; Transceivers Free Terms: MMW MMIC transceiver; IC packages; Ka-Band; Transmit/receive chips; Chip-to-chip/packaging interconnect; Chip-to-microstrip line/packaging interconnect; Chip-on-carrier design; Duroid; Soft substrate; RF circuit interconnection; IF amplification; 35 GHz Numerical Index: Frequency 3.5E+10 Hz Item Availability: CD-ROM. INSPEC 5218776 B9605-0170J-039 Doc Type: Conference Paper Title: Solderless interconnects for 3D microwave packaging Authors: Wooldridge, J. Affiliation: Hughes Aircraft Co., Los Angeles, CA, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 181-2 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Application; Practical; Experimental Abstract: The electrical performance parameters of solderless interconnects and the associated package development are reviewed for a 3D X-band transmit/receive module. The microwave performance over 7-18 GHz, as well as the environmental performance, are discussed with both theoretical and actual measurements. (0 Refs.) Classification: B0170J (Product packaging); B1350H (Microwave integrated circuits) Thesaurus: Integrated circuit interconnections; Integrated circuit packaging; Microwave integrated circuits; Modules Free Terms: Solderless interconnects; 3D microwave packaging; Electrical performance parameters; Package development; X-band; Transmit/receive module; Microwave performance; Environmental performance; 7 To 18 GHz Numerical Index: Frequency 7.0E+09 to 1.8E+10 Hz Item Availability: CD-ROM. INSPEC 5218761 B9605-7310N-005 Doc Type: Conference Paper Title: A coplanar waveguide probe with applications to thin film dielectric measurements Authors: Seltmann, E.W.; Laskar, J.; Smith, K.; Gleason, R. Affiliation: Sch. of Electron. Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 126-9 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Practical; Experimental Abstract: A novel approach to thin film dielectric measurements at microwave and millimeter wave frequencies is investigated using a coplanar waveguide (CPW) probe. Using the spectral-domain technique, an admittance model describing the CPW thin film interface system is determined for reflection measurement techniques, and delay measurement analysis is performed for thru measurement techniques. To validate the model, an error analysis is performed with 3D electromagnetic simulators and CPW S-parameter data from materials with known dielectric properties. (9 Refs.) Classification: B7310N (Microwave measurement techniques); B2810 (Dielectric materials and properties); B7310K (Dielectric variables measurement); B1320 (Waveguide components) Thesaurus: Coplanar waveguides; Delays; Dielectric measurement; Dielectric thin films; Microwave measurement; Millimetre wave measurement; Probes; S-parameters; Spectral-domain analysis Free Terms: Coplanar waveguide probe; Thin film dielectric measurements; Millimeter wave frequencies; Microwave frequencies; Spectral-domain technique; Admittance model; Reflection measurement techniques; Delay measurement analysis; Error analysis; 3D electromagnetic simulators; S-parameter data Item Availability: CD-ROM. INSPEC 5218752 B9605-0170J-030 Doc Type: Conference Paper Title: 255 CBGA electrical performance comparison through package electrical characterization and system simulations Authors: Osorio, R.; Casto, J. Affiliation: Motorola Inc., Chandler, AZ, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 95-7 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Theoretical/Mathematical; Experimental Abstract: The electrical performance of 255 CBGA packages from three suppliers are compared. This is done through the extraction of signal, power, and ground parasitic parameters such as resistance (R), self-inductance (L), mutual-inductance (M), and capacitance (C), and through SPICE system simulations. The results indicate that, although the three CBGAs` electrical performances were different, they all performed satisfactorily at 100 MHz bus-frequency, for a 2.0 ns through 0.5 ns rise/fall time. A similar behavior in electrical performance was observed at other frequencies. (0 Refs.) Classification: B0170J (Product packaging) Thesaurus: Capacitance; Circuit analysis computing; Circuit noise; Electric resistance; Inductance; Packaging; SPICE Free Terms: 255 CBGA packages; Electrical performance comparison; Electrical characterization; Bus-frequency; Parasitic parameters; Resistance; Self-inductance; Mutual-inductance; Capacitance; SPICE system simulations; Rise time; Fall time; 3D electromagnetic simulation; Transmitted noise; Power bounce; Ground bounce; Ceramic ball grid array; 100 MHz; 0.5 To 2 ns Numerical Index: Frequency 1.0E+08 Hz; Time 5.0E-10 to 2.0E-09 s Item Availability: CD-ROM. INSPEC 5218751 B9605-6320-010 Doc Type: Conference Paper Title: Test of 3D stacked microwave TR modules Authors: Hauhe, M.S. Affiliation: Hughes Aircraft Co., Los Angeles, CA, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 93-4 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Practical; Experimental Abstract: The performance of a three dimensional Transmit/Receive Module for a flat panel active array radar is reviewed. Solderless interconnects for both front and back side probing of the 3D Module are discussed as well as test results describing the performance of the module. (0 Refs.) Classification: B6320 (Radar equipment, systems and applications); B5270D (Antenna arrays); B0170J (Product packaging) Thesaurus: Active antenna arrays; Antenna testing; Heat sinks; Modules; Radar antennas; Transceivers Free Terms: 3D stacked microwave TR modules; Transmit/receive module; Flat panel active array radar; Solderless interconnects; Back side probing; Front side probing; Test results Item Availability: CD-ROM. INSPEC 5218747 B9605-5210-024 Doc Type: Conference Paper Title: LC: an integrated methodology to model and visualize the complex electrodynamics of 3D structures Authors: Gravrok, R.; Piket-May, M.; Thomas, K. Affiliation: Cray Res. Inc., Chippewa Falls, WI, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 73-6 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Theoretical/Mathematical Abstract: Equivalent-circuit models are obtained from direct interpretations of electromagnetic field data. Improved intuitive understanding is achieved with direct visualization of wave propagation through 3D structures. Applications to MCMs and power-distribution networks are described. (0 Refs.) Classification: B5210 (Electromagnetic wave propagation); B1130 (General circuit analysis and synthesis methods) Thesaurus: Electromagnetic wave propagation; Equivalent circuits Free Terms: LC; Electrodynamics; 3D structures; Equivalent-circuit model; Electromagnetic field; Visualization; Wave propagation; MCMs; Power-distribution networks Item Availability: CD-ROM. INSPEC 5218744 B9605-0170J-028 Doc Type: Conference Paper Title: Design method of a metallic enclosure considering EMI using a 3D-FEM Authors: Tanabe, S.; Nagano, N.; Itoh, T.; Murato, Y.; Mizukawa, S.; Sato, K. Affiliation: Mater. & Electron. Devices Lab., Mitsubishi Electr. Corp., Hyogo, Japan Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 64-6 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Practical; Theoretical/Mathematical Abstract: The leakage of electromagnetic radiation from a metallic enclosure with apertures is numerically analyzed by solving Maxwell`s equations directly using a three dimensional finite element method (3D-FEM). This method applied for designing a metallic enclosure for an asynchronous transfer mode digital service unit (ATM-DSU) to decrease EMI in the range of 30 MHz to 1 GHz. (1 Refs.) Classification: B0170J (Product packaging); B5230 (Electromagnetic compatibility and interference); B0290T (Finite element analysis) Thesaurus: Electromagnetic interference; Finite element analysis; Maxwell equations; Packaging Free Terms: Metallic enclosure; EMI; 3D-FEM; Electromagnetic radiation leakage; Apertures; Maxwell`s equations; Asynchronous transfer mode digital service unit; ATM-DSU; 30 MHz to 1 GHz Numerical Index: Frequency 3.0E+07 to 1.0E+09 Hz Item Availability: CD-ROM. INSPEC 5218737 B9605-2210B-005 C9605-7410D-094 Doc Type: Conference Paper Title: Computation of switching noise in PCBs for digital packages Authors: Jong-Gwan Yook; Chandramouli, V.; Katehi, L.P.; Sakallah, K.A. Affiliation: Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.95TH8137) p. 37-9 Publisher: IEEE New York, NY, USA Date: 1995 viii+240 pp. Country of Publication: USA ISBN: 0 7803 3034 X CCC: 0 7803 3034 X/95/$4.00 Language: English Conf. Date: 2-4 Oct. 1995 Conf. Loc: Portland, OR, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc.; IEEE Components, Packaging & Manuf. Technol. Soc Treatment: Practical; Theoretical/Mathematical Abstract: Simultaneous switching noise in printed circuit boards for digital packages is computed using a hybrid technique which combines electromagnetic analysis (3D FEM) and circuit simulation (HSPICE) for fast and efficient time and frequency domain analysis. (6 Refs.) Classification: B2210B (Printed circuit layout and design); B1130B (Computer-aided circuit analysis and design); B0170J (Product packaging); B0290T (Finite element analysis); C7410D (Electronic engineering computing); C4185 (Finite element analysis) Thesaurus: Circuit analysis computing; Circuit noise; Finite element analysis; Frequency-domain analysis; Packaging; Printed circuit design; SPICE; Time-domain analysis Free Terms: Switching noise; PCBs; Digital packages; Printed circuit boards; Electromagnetic analysis; 3D FEM; Circuit simulation; HSPICE; Frequency domain analysis; Time domain analysis Item Availability: CD-ROM. INSPEC 5211954 B9604-1265B-087 C9604-5210B-035 Doc Type: Conference Paper Title: Testability controlled physical design of vertically stacked integrated circuits Authors: Reber, M.; Kirsch, A. Affiliation: Inst. for Electron., Kaiserslautern Univ., Germany Conf. Title: Proceedings Eighth Annual IEEE International ASIC Conference and Exhibit (Cat. No.95TH8087) p. 249-52 Editors: Cook, W.A.; Hull, R.A.; Traver, C. Publisher: IEEE New York, NY, USA Date: 1995 xv+422 pp. Country of Publication: USA ISBN: 0 7803 2707 1 CCC: 0 7803 2707 1/95/$4.00 Language: English Conf. Date: 18-22 Sept. 1995 Conf. Loc: Austin, TX, USA Treatment: Practical Abstract: Vertical integration technology is expected to provide several advantages, such as high packaging density, parallel processing, high speed operation and an improved reliability. Basic design aspects for vertically stacked integrated circuits are discussed in this paper. A novel partitioning method for vertically stacked integrated circuits (VIC) will be proposed which generates testable circuit partitions. Generated circuit layouts of partitioned MCNC benchmark circuits demonstrate the superiority of 3-D circuit layouts over planar circuit layouts especially for increased circuit sizes. (6 Refs.) Classification: B1265B (Logic circuits); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B0170N (Reliability); B1130B (Computer-aided circuit analysis and design); C5210B (Computer-aided logic design); C7410D (Electronic engineering computing) Thesaurus: Application specific integrated circuits; Circuit layout CAD; Circuit optimisation; Design for testability; Integrated circuit design; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit reliability; Logic CAD; Logic partitioning Free Terms: Testability controlled physical design; Vertically stacked integrated circuits; Packaging density; Parallel processing; High speed operation; Reliability; Design aspects; Partitioning method; Testable circuit partitions; Circuit layouts; MCNC benchmark circuits; 3D circuit layouts; Circuit sizes Item Availability: CD-ROM. INSPEC 5202215 B9604-7230G-018 C9604-3240K-004 Doc Type: Journal Paper Title: Airborne ultrasonic imaging system for parallelepipedic object localization Authors: Ossant, F.; Poisson, G.; Tran-Huu-Hue, L.P.; Roncin, A.; Lethiecq, M. Affiliation: Fac. de Medecine, GIP Ultrasons, Tours, France Journal: IEEE Transactions on Instrumentation and Measurement Vol: 45 Iss: 1 p. 107-11 Publisher: IEEE Date: Feb. 1996 Country of Publication: USA ISSN: 0018-9456 CODEN: IEIMAO CCC: 0018-9456/96/$05.00 Language: English Treatment: Application; Practical Abstract: An ultrasonic image device was designed for use in robotic applications where parallelepipedic objects need to be manipulated. It is based on ranging measurement by an array of ten identical airborne ultrasonic transducers with an operating frequency of 200 kHz and a detection cone angle of approximately 7 degrees. An electronic scanning associated with a mechanical displacement of the array covers an area of 0.4*0.4 m in less than 0.5 seconds (100 measurement points). The system was tested in an automatic packaging line. It allowed a real-time localization of cubic objects as small as 2 cm and the determination of an emplacement in which a new object can be put by a robot arm. (7 Refs.) Classification: B7230G (Image sensors); B7810C (Sonic and ultrasonic transducers); C3240K (Image sensors); C3390 (Robotics) Thesaurus: Industrial robots; Ultrasonic imaging; Ultrasonic transducer arrays Free Terms: Airborne ultrasonic imaging; Parallelepipedic object localization; Robotic applications; Ranging measurement; Cross coupling; Airborne ultrasonic transducers; Detection cone angle; Electronic scanning; Mechanical displacement; Measurement points; Automatic packaging line; Real-time localization; Cubic objects; Robot arm; 3D perception; 200 KHz; 0.4 M; 2 Cm Numerical Index: Frequency 2.0E+05 Hz; Distance 4.0E-01 m; Size 2.0E-02 m Item Availability: CD-ROM. INSPEC 5163460 C9603-5490-002 Doc Type: Journal Paper Title: Heat-transfer engineering in systems integration: outlook for closer coupling of thermal and electrical designs of computers Authors: Nakayama, W. Affiliation: Dept. of Mech. & Intelligent Syst. Eng., Tokyo Inst. of Technol., Japan Journal: IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A Vol: 18 Iss: 4 p. 818-26 Publisher: IEEE Date: Dec. 1995 Country of Publication: USA ISSN: 1070-9886 CODEN: IMTAEZ CCC: 1070-9886/95/$04.00 Language: English Treatment: Practical Abstract: This paper begins with a review of the author`s personal experience in the research field of computer cooling. It highlights the need to develop foresight on the possible course of hardware development in order to provide the package designer with appropriate heat-transfer data in a timely manner. A question is then raised about the immediate future of the (indirect) water-cooling technology. Water-cooling has so far proven effective in cooling high-end computers which use ECL devices in two-dimensional packaging. The drive toward higher raw speeds of ECL devices, however, is going to lose steam-emerging instead is the endeavor to upgrade system performance by massively-parallel computing which requires wiring-intensive hardware. Three-dimensional packaging will meet the demand for short global wiring in systems, but will become a commercial reality only after the establishment of methodologies for its design and assembling. One of the key issues in the design of 3-D computers is the optimum allocation of physical space for electrical wiring and heat-transfer paths. Intimate coupling of wiring and heat transfer designs pose challenges to heat-transfer researchers that have not surfaced in other industrial applications. Items of primary importance include: the methodology to predict how and temperature distributions in a field having a wide spectrum of length scales, the local heat-transfer coefficients in the maze of microscale coolant channels, the possibly large effect of extraneous factors such as irregular geometric features of coolant channels and conjugate mode of heat transfer, and temperature control during assembling of 3-D structures. (34 Refs.) Classification: C5490 (Other aspects of analogue and digital computers) Thesaurus: Computers; Cooling; Design engineering; Packaging; Systems engineering Free Terms: Heat-transfer engineering; Systems integration; Thermal design; Electrical design; Computer cooling; Water-cooling; ECL devices; Massively-parallel computing; Three-dimensional packaging; Electrical wiring; Two-dimensional packaging; Temperature distribution; Temperature control Item Availability: CD-ROM. INSPEC 5158269 B9602-2250-007 Doc Type: Journal Paper Title: Utilizing a low cost 3D packaging technology for consumer applications Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, L. Affiliation: Dept. of Electron. & Electr. Eng., Sheffield Univ., UK Journal: IEEE Transactions on Consumer Electronics Vol: 41 Iss: 4 p. 1095-102 Publisher: IEEE Date: Nov. 1995 Country of Publication: USA ISSN: 0098-3063 CODEN: ITCEDA CCC: 0098-3063/95/$04.00 Language: English Treatment: Application; New development; Practical Abstract: This paper demonstrates how a low cost three-dimensional packaging (multichip module-vertical) technology can be utilized to implement systems for consumer applications. In any application where system cost, volume and mass are important, this packaging technique can be advantageous, particularly in the rapidly growing portable electronics industry. To illustrate this we present a general-purpose, low-cost camera and image processing system in the new packaging technology. This can be used in multimedia, surveillance and smart vision applications. (7 Refs.) Classification: B2250 (Multichip modules); B6210R (Multimedia communications); B6140C (Optical information, image and video signal processing); B7230 (Sensing devices and transducers); B6430H (Video recording); B0170J (Product packaging) Thesaurus: Consumer electronics; Image processing; Intelligent sensors; Multichip modules; Multimedia systems; Surveillance; Video cameras Free Terms: Low cost 3D packaging technology; Consumer applications; System cost; Volume; Mass; Portable electronics industry; Low-cost camera; Image processing system; Smart vision applications; Surveillance applications; Multimedia applications; Multichip module-vertical; Portable video communicator Item Availability: CD-ROM. INSPEC 5133644 B9601-2210-010 Doc Type: Journal Paper Title: A novel type of low dielectric and heat-resistant resin for printed wiring boards Authors: Nawa, K.; Ohkita, M. Affiliation: Sumitomo Metal Ind. R&D Center, Hyogo, Japan Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 18 Iss: 4 p. 691-6 Date: Nov. 1995 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/95/$04.00 Language: English Treatment: Application; New development; Practical; Experimental Abstract: We developed a novel type of low dielectric and heat-resistant resin. The resin was synthesized from dehydrating reaction between fused aromatics and 1,4-benzenedimethanol, therefore, it was called advanced polyCOndensed fused PolyNuclear Aromatic Resin (advanced COPNA-Resin). The advanced COPNA-Resin exhibited characteristic properties for an electrical insulator: e.g., high Tg (250 degrees C), low dielectric constant (3.1 for 1 MHz), and low water absorption (0.37 wt.%). We studied fabrication and properties of prepregs, double-sided copper-clad laminates, printed wiring boards with copper-plated through-holes using advanced COPNA-Resin as an insulating material. Prepregs were fabricated by the dipping process of E-glass or T-glass fiber woven fabrics into the resin solution. Copper-clad laminates were obtained by hot-press fabrication of advanced COPNA-Resin prepregs. The laminates reinforced by E-glass fiber woven fabric exhibited characteristic properties for multilaying printed wiring boards. Tg was 255 degrees C. The dielectric constant was 4.2. Advanced COPNA-Resin laminates exhibited higher Tg and lower dielectric constant than polyimide laminates known as heat-resistant and low dielectric materials. The linear thermal expansion coefficient of advanced COPNA-Resin laminates for xy-axis was 4-5 ppm, and that for z-axis was 29 ppm. Advanced COPNA-Resin printed wiring board exhibited outstanding reliability of electrical connection of copper-plated through-holes in comparison with the epoxy or the polyimide system. From those analysis for Tg, dielectric constant, linear thermal expansion coefficients, and through-hole reliability, the advanced COPNA-Resin was regarded as novel type of advanced material for high-density interconnects such as fine-pitch surface mount and multichip modules. (13 Refs.) Classification: B2210 (Printed circuits); B0560 (Polymers and plastics (engineering materials science)); B0550 (Composite materials (engineering materials science)); B0170N (Reliability); B2830C (Organic insulation); B2810 (Dielectric materials and properties) Thesaurus: Circuit reliability; Hot pressing; Laminates; Materials preparation; Organic insulating materials; Permittivity; Polymers; Printed circuits; Surface mount technology; Thermal expansion Free Terms: Low dielectric constant resin; Heat-resistant resin; Printed wiring boards; Dehydrating reaction; Fused aromatics; 1,4-Benzenedimethanol; Polycondensed fused polynuclear aromatic resin; Advanced COPNA-Resin; Low water absorption; Fabrication; Prepregs; Double-sided Cu-clad laminates; Cu plated through-holes; PTH PWB; MCM mounting; Fine-pitch SMD; High-density interconnects; Through-hole reliability; Linear thermal expansion coefficients; E-glass fiber woven fabric; Hot-pressing; Dipping process; 250 C; 255 C; Cu Numerical Index: Temperature 5.23E+02 K; Temperature 5.28E+02 K Chemical Index: Cu/int Cu/el Item Availability: CD-ROM. INSPEC 5118447 B9601-0170J-007 C9601-5490-001 Doc Type: Conference Paper Title: Three dimensional stacking with diamond sheet heat extraction for subnanosecond machine design Authors: McDonald, J.F.; Greub, H.E.; Campbell, P.; Maier, C.; Garg, A.; Steidl, S. Affiliation: Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1995 Proceedings. Seventh Annual IEEE International Conference on Wafer Scale Integration (Cat. No.95CH3574-2) p. 62-71 Publisher: IEEE New York, NY, USA Date: 1995 ix+382 pp. Country of Publication: USA ISBN: 0 7803 2467 6 CCC: 0 7803 2466 8/95/$4.00 Language: English Conf. Date: 18-20 Jan. 1995 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Comput. Soc.; IEEE Components, Packaging, & Manuf. Technol. Soc Treatment: Practical Abstract: Devices are becoming available whose inherent switching speeds are approaching only a few picoseconds. CMOS FET devices with 0.12 micron channel length have exhibited f/sub T/ values of 89 GHz. SiGe HBTs have been demonstrated with an f/sub T/ of 117 GHz. InP/InGaAs/AlGaAs HBT's have exhibited an f/sub T/ of 200 GHz, with minimum feature sizes that are above one micron. InGaAs/AlGaAs MESFET's with 0.05 micron channel lengths have exhibited f/sub T/ values of 350 GHz. Clearly even faster devices are possible, and some have even begun to appear in viable fabrication lines where prospects for interesting levels of integration are being realized. For such technologies subnanosecond machine cycles seem possible. However, for conventional 2D chip or wafer fabrication some of the distances between key components on these substrates can be too long for subnanosecond operation. This may be true even for ideal transmission line interconnections that exhibit 'speed of light' propagation speeds and extremely wide bandwidths. At this point the last resort is to shorten these interconnections by rearranging the components in 3D structures, implying either die or wafer stacking. This paper explores some of the requirements for subnanosecond machine design, and practical schemes to accomplish this with discussion on how to distribute the power supply current and dissipate the heat generated. These schemes use the full array of WSI, WSHP and MCM technologies plus some new techniques for 3D vertical stacking. (0 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); C5490 (Other aspects of analogue and digital computers) Thesaurus: Cooling; Diamond; Heat sinks; Multichip modules; Wafer-scale integration Free Terms: Three dimensional stacking; Diamond sheet heat extraction; Subnanosecond machine design; CMOS FET devices; SiGe HBTs; InP/InGaAs/AlGaAs HBTs; InGaAs/AlGaAs MESFETs; Integration; Transmission line interconnections; Die stacking; Wafer stacking; Power supply current distribution; Vertical stacking; WSI; WSHP; MCM; Switching speeds; Fabrication; C Chemical Index: C/el Item Availability: CD-ROM. INSPEC 5112914 B9512-2570A-025 C9512-7410D-195 Doc Type: Conference Paper Title: Chip-level thermal simulator to predict VLSI chip temperature Authors: Yi-Kan Cheng; Sung-Mo Kang Affiliation: Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA Conf. Title: 1995 IEEE Symposium on Circuits and Systems (Cat. No.95CH35771) p. 1392-5 vol.2 Publisher: IEEE New York, NY, USA Date: 1995 3 vol. l+2346 pp. Country of Publication: USA ISBN: 0 7803 2570 2 CCC: 0 7803 2570 2/95/$4.00 Language: English Conf. Date: 28 April-3 May 1995 Conf. Loc: Seattle, WA, USA Conf. Sponsor: IEEE Circuits & Syst. Soc Treatment: Theoretical/Mathematical Abstract: In this paper, a new thermal simulator is developed to predict the steady-state and transient temperatures inside a VLSI chip subjected to heating by single or multiple heat sources. It uses a mixed 3D finite-difference and 1D analogous thermal circuit method, taking into account any combination of boundary conditions, shape of heat sources, and packaging. An analytical method is also presented and compared to the numerical method. With this tool, the chip temperature can be predicted accurately to provide design guidelines for VLSI module placement and chip packaging. (5 Refs.) Classification: B2570A (Integrated circuit modelling and process simulation); B0170J (Product packaging); B0290P (Differential equations); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing); C4170 (Differential equations) Thesaurus: Circuit analysis computing; Finite difference methods; Integrated circuit modelling; Integrated circuit packaging; Temperature distribution; Thermal analysis; VLSI Free Terms: Chip-level thermal simulator; VLSI chip temperature prediction; Steady-state temperature; Transient temperature; Multiple heat sources; Single heat source; 3D finite-difference method; 1D analogous thermal circuit method; Analytical method; Numerical method; Module placement; Chip packaging Item Availability: CD-ROM. INSPEC 5057087 B9511-0170J-016 C9511-7410D-033 Doc Type: Conference Paper Title: Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures Authors: Silveira, L.M.; Kamon, M.; White, J. Affiliation: Res. Lab. of Electron., MIT, Cambridge, MA, USA Conf. Title: Proceedings. The European Design and Test Conference. ED&TC 1995 (Cat. No.95TH8058) p. 534-8 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1995 xxvii+611 pp. Country of Publication: USA ISBN: 0 8186 7039 8 CCC: 1066 1409/95/$4.00 Language: English Conf. Date: 6-9 March 1995 Conf. Loc: Paris, France Conf. Sponsor: IEEE Comput. Soc.; EDA Assoc.; Eur. Group of TTC & the DATC; ACM/SIGDA Treatment: Theoretical/Mathematical Abstract: Reduced-order modeling techniques are now commonly used to efficiently simulate circuits combined with interconnect, but generating reduced-order models from realistic 3-D structures has received less attention. In this paper we describe a Krylov-subspace based method for deriving reduced-order models directly from the 3-D magnetoquasistatic analysis program FASTHENRY. This new approach is no more expensive than computing an impedance matrix at a single frequency. (11 Refs.) Classification: B0170J (Product packaging); B0290F (Interpolation and function approximation); C7410D (Electronic engineering computing); C4130 (Interpolation and function approximation) Thesaurus: Electronic engineering computing; Inductance; Integrated circuit interconnections; Integrated circuit packaging; Iterative methods; Modelling; State-space methods Free Terms: Reduced-order modeling; Frequency-dependent coupling inductances; 3D interconnect structures; Krylov-subspace based method; 3D magnetoquasistatic analysis program; FASTHENRY Item Availability: CD-ROM. INSPEC 5033354 B9510-0170J-024 Doc Type: Conference Paper in Journal Title: Compliant bumps for adhesive flip-chip assembly Authors: Keswick, K.; German, R.L.; Breen, M.; Nolan, R. Affiliation: Microelectron. & Comput. Technol. Corp., Austin, TX, USA Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 18 Iss: 3 p. 503-10 Date: Aug. 1995 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 Language: English Conf. Title: 44th Electronic Components and Technology Conference Conf. Date: 1-4 May 1994 Conf. Loc: Washington, DC, USA Treatment: Practical; Experimental Abstract: Flip-chip-on-glass (FCOG) is susceptible to electrical opens for a variety of reasons including, but not limited to, movement in the Z-axis caused by flip-chip, adhesive CTE and water absorption of the adhesive. Flip-chip assembly to co-fired ceramic and laminate substrates suffers from these problems as well as others, such as bow or twist in the substrate and bond pad height irregularities. Success with adhesive flip-chip connections to these substrates has, to date, been limited. Commercially available adhesives have either failed to produce reliable bonds, or have suffered from long cure time or a lack of reworkability. A solution to these problems has been demonstrated by forming compliant bumps on the chip or substrate bond pads using a photo-imagable polymer coated with a thin layer of gold. Bumps 17 mu m tall with diameters between 17 mu m and 95 mu m have been fabricated and bonded. The resulting compliant bump structure provides 30% of the bump height (5 mu m) within the elastic compression range. This compliance eliminates many of the demands placed on the assembly adhesives by other electrical contacting methods (such as solid metal bumps or particles). Compliant bumps allow the use of commercially available, fast curing, easily reworkable adhesives for reliable flip-chip assembly. MCC's compliant bumps have been mechanically cycled from minimum compression (needed for electrical contact) to maximum compression (based on diminishing compression distance versus applied force) 1000 times, with minimal degradation of the polymer core or metal overcoat. Assemblies have been subjected to temperature cycling and steam pot aging with substantial improvement in reliability when compared to assemblies using solid metal bumps. Using compliant bump technology, low temperature rework has been demonstrated with compliant bumped chips on glass, laminate and MCM-C substrates. Chips or substrates with compliant bumps are re-usable, a significant advantage over conventional gold bump processes where the bump structure is permanently deformed by the bonding process. (4 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B0170E (Production facilities and engineering); B0170N (Reliability); B2250 (Multichip modules) Thesaurus: Ageing; Flip-chip devices; Integrated circuit reliability; Life testing; Multichip modules; Tape automated bonding Free Terms: Adhesive flip-chip assembly; Compliant bumps; Substrate bond pads; Photoimagible polymer; Bump height; Elastic compression range; Assembly adhesive; Reworkable adhesives; Compression distance; Temperature cycling; Steam pot aging; Low temperature rework; Glass substrates; Laminate substrates; MCM-C substrates; Bonding process; 17 To 95 micron Numerical Index: Size 1.7E-05 to 9.5E-05 m Item Availability: CD-ROM. INSPEC 5027114 B9510-0170J-008 Doc Type: Conference Paper Title: BGA inspection (Abstract) Authors: Rideout, E. Affiliation: RVSI, Hauppauge, NY, USA Conf. Title: Sixteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Low-Cost Manufacturing Technologies for Tomorrow's Global Economy'. Proceedings 1994 IEMT Symposium (Cat. No.94CH3473-6) p. 388 vol.1 Publisher: IEEE New York, NY, USA Date: 1994 2 vol. (xii+404+viii+104 pp.) Country of Publication: USA ISBN: 0 7803 2037 9 CCC: 0 7803 2037 9/94/$3.00 Language: English Conf. Date: 12-14 Sept. 1994 Conf. Loc: La Jolla, CA, USA Conf. Sponsor: Electron. Ind. Assoc.; IEEE Components Packaging & Manuf. Technol. Soc Treatment: Practical; Experimental Abstract: Summary form only give as follows. BGAs (Ball Grid Arrays) have drawn much attention as the rising star of high-pincount surface mount packaging technology. Compared to fine-pitch QFPs they offer: a higher pincount for a given area, the ability to use existing or at least less costly mounting equipment, and lower solder defect rates. Disadvantages are a higher package cost and the inability to inspect the solder joints after reflow. It has been argued that the cost disadvantage goes away when overall manufacturing costs through finished product are taken into account. The problem of not being able to physically inspect the solder joints may never go away. However, one can mitigate the need to inspect solder joints by physical inspection of the BGA prior to mounting. This paper discusses the physical attributes of a BGA which contribute to poor mounting and how 3-D laser inspection can be used to check those attributes. The presentation focuses on the use of a laser system to measure coplanarity, true position error, pitch, ball diameter, and board warpage. Also addressed are issues associated with inspection of BGAs as presented to the placement system. Future applications of 3-D inspection are mentioned. (0 Refs.) Classification: B0170J (Product packaging); B0170L (Inspection and quality control); B4360 (Laser applications) Thesaurus: Inspection; Integrated circuit packaging; Laser beam applications; Soldering; Surface mount technology Free Terms: BGAs; Ball grid arrays; High-pincount surface mount packaging technology; Mounting equipment; Solder defect rates; Package cost; Solder joint inspection; 3D laser inspection; Coplanarity; True position error; Ball diameter; Board warpage; Placement system Item Availability: CD-ROM. INSPEC 5027113 B9510-0170J-007 Doc Type: Conference Paper Title: 3-D packaging-applications of vertical multichip modules (MCM-V) for microsystems Authors: Val, C. Affiliation: Thomson-CSF, Colombes, France Conf. Title: Sixteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Low-Cost Manufacturing Technologies for Tomorrow's Global Economy'. Proceedings 1994 IEMT Symposium (Cat. No.94CH3473-6) p. 387 vol.1 Publisher: IEEE New York, NY, USA Date: 1994 2 vol. (xii+404+viii+104 pp.) Country of Publication: USA ISBN: 0 7803 2037 9 CCC: 0 7803 2037 9/94/$3.00 Language: English Conf. Date: 12-14 Sept. 1994 Conf. Loc: La Jolla, CA, USA Conf. Sponsor: Electron. Ind. Assoc.; IEEE Components Packaging & Manuf. Technol. Soc Treatment: Application; Practical Abstract: Summary form only given. Classical 2-dimensional interconnection is compared to microtechniques using the 3rd dimension. Since 1989, several European projects with large companies including Alcatel, Daimler-Benz, Geo-Marconi, SGS Thomson, and several European universities, and Thomson-CSF have demonstrated, evaluated, and qualified the 3-D technique. The results of qualification are presented from 150 technology demonstrations plus 100 memory modules. The three-dimensional interconnection technology is presented for five application groups. (0 Refs.) Classification: B0170J (Product packaging); B2250 (Multichip modules) Thesaurus: Integrated circuit interconnections; Integrated circuit packaging; Multichip modules Free Terms: 3D packaging; Vertical multichip modules; MCM-V; Qualification; Memory modules; Technology demonstrations; Three-dimensional interconnection technology Item Availability: CD-ROM. INSPEC 5022802 B9509-7220-019 C9509-5530-017 Doc Type: Conference Paper Title: A micro-packaged image acquisition and processing module Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, N.L.; Shelley, A.J. Affiliation: Sheffield Univ., UK Conf. Title: Fifth International Conference on Image Processing and its Applications (Conf. Publ. No.410) p. 455-9 Publisher: IEE London, UK Date: 1995 xxii+857 pp. Country of Publication: UK ISBN: 0 85296 642 3 Language: English Conf. Date: 4-6 July 1995 Conf. Loc: Edinburgh, UK Treatment: Practical Abstract: The paper describes a prototype module, which is an image acquisition and processing pipeline implemented in a micro-package. The module converts incident light directly to processed digital video data. The system is packaged using a novel three-dimensional technology called MCM-V (multichip module-vertical), Val (1991). This technology stacks integrated circuits in the z-axis to produce dense systems. The module is fully programmable and can be used in a wide range of image processing tasks. The results presented form the first stage in the development of high performance ultra-miniature camera and image processing systems. (8 Refs.) Classification: B7220 (Signal processing and conditioning equipment and techniques); B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B2250 (Multichip modules); B6430H (Video recording); C5530 (Pattern recognition and computer vision equipment); C5135 (Digital signal processing chips); C5220P (Parallel architecture) Thesaurus: Application specific integrated circuits; Digital signal processing chips; Image processing equipment; Multichip modules; Parallel architectures; Pipeline processing; Transputers; Video cameras; Video signal processing; VLSI Free Terms: Micro-packaged image acquisition; Processing module; Prototype module; Processed digital video data; Three-dimensional technology; MCM-V; Multichip module-vertical; Integrated circuits; Z-axis; Dense systems; Fully programmable module; High performance ultra-miniature camera Item Availability: CD-ROM. INSPEC 5022531 B9509-2560J-036 Doc Type: Conference Paper Title: 3D FDTD analysis of a SOT353 package containing a bipolar wideband cascode transistor using the compression approach Authors: Rittweger, M.; Werthen, M.; Kunisch, J.; Wolff, I.; Chall, P.; Balm, B.; Lok, P. Affiliation: Inst. fur Mobil-und Satellitenfunktechnik, Kamp-Lintfort, Germany Conf. Title: 1995 IEEE MTT-S International Microwave Symposium Digest (Cat. No.95CH3577-4) p. 1587-90 vol.3 Editors: Kirby, L. Publisher: IEEE New York, NY, USA Date: 1995 3 vol. (lxxi+xli+1714 pp.) Country of Publication: USA ISBN: 0 7803 2581 8 CCC: CH3577-4/95/0000-1587$01.00 Language: English Conf. Date: 16-20 May 1995 Conf. Loc: Orlando, FL, USA Treatment: Theoretical/Mathematical Abstract: A 3d electromagnetic simulation of an entire mold injected plastic package including its coplanar environment is presented. The active elements are substituted by inner ports. The resulting network is connected with measured transistor data using a circuit simulator. A comparison of the simulated data with measured results is shown. The influence of the package and therefore the meaning of such a simulation procedure is discussed. (5 Refs.) Classification: B2560J (Bipolar transistors); B1350F (Solid-state microwave circuits and devices); B0170J (Product packaging); B0290Z (Other numerical methods) Thesaurus: Finite difference time-domain analysis; Microwave bipolar transistors; Plastic packaging; Semiconductor device packaging Free Terms: 3D FDTD analysis; SOT353 package; Bipolar wideband cascode transistor; Compression; Electromagnetic simulation; Mold injected plastic package; Coplanar environment; Active elements; Inner ports; Network; Circuit simulator Item Availability: CD-ROM. INSPEC 4999836 B9509-0170J-001 Doc Type: Journal Paper Title: Thermal-mechanical enhanced high-performance silicone gels and elastomeric encapsulants in microelectronic packaging Authors: Wong, C.P. Affiliation: AT&T Bell Labs., Princeton, NJ, USA Journal: IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A Vol: 18 Iss: 2 p. 270-3 Date: June 1995 Country of Publication: USA ISSN: 1070-9886 CODEN: IMTAEZ CCC: 1070-9886/95/$04.00 Language: English Treatment: Application; Experimental Abstract: A modern electronic device is a complex 3-D structure that consists of millions of components for each single integrated circuit (IC) chip. This complex and delicate device requires effective encapsulation and packaging to ensure its long-term reliability. This device encapsulant requires not only excellent electrical and physical properties, but also suitable mechanical properties for hostile and extreme temperature cycling requirements (from -65 degrees to 150 degrees C). Hence, the mechanical and thermal behavior of the encapsulant plays a critical role in device reliability. Low stress encapsulants are the preferred choice for microelectronic packaging. Silicone-based materials, either the elastomers or gels, with their low modulus and excellent electrical properties, are the best encapsulants. However, the intrinsic low modulus silicone provides weak mechanic protection for the IC device. We have, however, modified the silicone material with a high loading of silica to improve its mechanical and physical properties. This high-silica filler loading material improves not only its mechanical property, but also its modulus. Furthermore, this modified high modulus silicone material tends to have microcracks during the high temperature thermal cycling testing that generates the device reliability problem. In this paper, we will describe a modified version of the thermal-mechanical enhanced silicone-based encapsulant, its material formulation, curing process, thermal mechanical failure and its protecting mechanisms, and its application. (15 Refs.) Classification: B0170J (Product packaging); B2220 (Integrated circuits); B2570 (Semiconductor integrated circuits); B0170N (Reliability); B0560 (Polymers and plastics (engineering materials science)) Thesaurus: Encapsulation; Filled polymers; Gels; Integrated circuit packaging; Integrated circuit reliability; Mechanical properties; Polymer films; Silicones; Thermal stability; Thermal stress cracking; Thermal stresses Free Terms: Silicone gels; Elastomeric encapsulants; Microelectronic packaging; Integrated circuit chip; Encapsulation; Mechanical properties; Long-term reliability; Silica loaded material; High modulus silicone material; Curing process; Thermal-mechanical failure; Protecting mechanisms; Siloxane polymer; -65 To 150 C Numerical Index: Temperature 2.08E+02 to 4.23E+02 K Item Availability: CD-ROM. INSPEC 4997899 B9508-6320-040 Doc Type: Conference Paper Title: High density microwave packaging for T/R modules Authors: Wooldridge, J. Affiliation: Hughes Aircraft Co., El Segundo, CA, USA Conf. Title: 1995 IEEE MTT-S International Microwave Symposium Digest (Cat. No.95CH3577-4) p. 181-4 vol.1 Editors: Kirby, L. Publisher: IEEE New York, NY, USA Date: 1995 3 vol. (lxxi+xli+1714 pp.) Country of Publication: USA ISBN: 0 7803 2581 8 Language: English Conf. Date: 16-20 May 1995 Conf. Loc: Orlando, FL, USA Treatment: Application; Practical Abstract: This paper describes the development of low cost 3-D packaging of transmit/receive (T/R) modules for an active array radar at X-band. The development focused on the design, manufacture and interconnection of multi-layer aluminum nitride (AlN) substrates. The substrates are electrically joined together with solderless interconnects. All GaAs and most silicon chips have been flipped for achieving low cost assembly and higher reliability. The major microwave transmission line is conductor backed coplanar line CBCPW which interfaces with the coplanar line used on the flipped microwave chip. The interconnect technology is applicable to commercial high speed data lines that are concerned about preserving the fast rise time of the signal. (0 Refs.) Classification: B6320 (Radar equipment, systems and applications); B0170J (Product packaging); B2240 (Microassembly techniques); B0170E (Production facilities and engineering) Thesaurus: Coplanar waveguides; Electronic equipment manufacture; Flip-chip devices; Integrated circuit interconnections; Microassembling; Modules; Packaging; Phased array radar; Radar equipment Free Terms: High density microwave packaging; T/R modules; Low cost 3D packaging; Transmit/receive modules; Active array radar; X-band; Multilayer AlN substrates; Solderless interconnects; Flip-chip assembly; Low cost assembly; Conductor backed coplanar line; Flipped microwave chips; AlN; GaAs; Si Chemical Index: AlN/sur Al/sur N/sur AlN/bin Al/bin N/bin; GaAs/int As/int Ga/int GaAs/bin As/bin Ga/bin; Si/int Si/el Item Availability: CD-ROM. INSPEC 4955614 B9507-0170J-018 Doc Type: Conference Paper Title: Preconditioning for multipole-accelerated 3-D inductance extraction Authors: Kamon, M.; White, J. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.93TH0586-8) p. 189-92 Publisher: IEEE New York, NY, USA Date: 1993 vii+238 pp. Country of Publication: USA ISBN: 0 7803 1427 1 CCC: 0 7803 1427 1/93/$3.00 Language: English Conf. Date: 20-22 Oct. 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc Treatment: Theoretical/Mathematical Abstract: Frequency-dependent inductances and resistances of complicated 3-D packages can be extremely efficiently computed using a volume-element formulation combined with a multipole-accelerated iterative matrix solution method, provided the iterative method converges rapidly. Two approaches to preconditioning the iterative method are presented, and results are given which show that both methods substantially accelerate iterative method convergence when applied to the inductance extraction problem. (5 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B0290F (Interpolation and function approximation) Thesaurus: Convergence of numerical methods; Inductance; Integrated circuit packaging; Iterative methods; Matrix algebra Free Terms: 3D packages; 3D inductance extraction; GMRES; Integrated circuit; Frequency dependent resistance; Preconditioning; Volume-element formulation; Multipole-accelerated iterative matrix solution method; Iterative method convergence Item Availability: CD-ROM. INSPEC 4955599 B9507-5230-003 Doc Type: Conference Paper Title: Efficient computation of ground plane inductances and currents Authors: Raghuram, R.; Divekar, D.; Wang, P. Affiliation: CONTEC Microelectronics, San Jose, CA, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.93TH0586-8) p. 131-4 Publisher: IEEE New York, NY, USA Date: 1993 vii+238 pp. Country of Publication: USA ISBN: 0 7803 1427 1 CCC: 0 7803 1427 1/93/$3.00 Language: English Conf. Date: 20-22 Oct. 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc Treatment: Theoretical/Mathematical Abstract: An efficient method for calculating an inductance subcircuit from a 3-D geometry containing reference planes is presented. The complexity is reduced to O(n/sup 2/log(n)) compared to O(n/sup 6/) for a direct implementation. (6 Refs.) Classification: B5230 (Electromagnetic compatibility and interference); B0170J (Product packaging); B2570 (Semiconductor integrated circuits) Thesaurus: Electric current; Electromagnetic interference; Fast Fourier transforms; Inductance; Integrated circuit packaging; SPICE Free Terms: Ground plane current; 3D geometry; SPICE; FFT; EMI; Integrated circuits; Ground plane inductances; Inductance subcircuit Item Availability: CD-ROM. INSPEC 4955597 B9507-0170J-011 Doc Type: Conference Paper Title: Exploiting symmetry in the extraction of electrical packaging parameters Authors: Huang, C.-C. Affiliation: IBM Raleigh, Research Triangle Park, NC, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.93TH0586-8) p. 125-7 Publisher: IEEE New York, NY, USA Date: 1993 vii+238 pp. Country of Publication: USA ISBN: 0 7803 1427 1 CCC: 0 7803 1427 1/93/$3.00 Language: English Conf. Date: 20-22 Oct. 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc Treatment: Theoretical/Mathematical Abstract: The author examines three different aspects of exploiting a structure's symmetry to efficiently compute electrical packaging parameters: (a) recognizing the cross-sectional symmetry eases the numerical integration of 3-D partial inductances; (b) the direct inversion of a partial impedance matrix lets one take advantage of a structure's symmetry in computing resistance and inductance matrices of uniformly coupled transmission lines; and (c) an almost symmetric and/or periodic structure can be either decomposed or augmented to exploit the special property of its corresponding system matrix. (7 Refs.) Classification: B0170J (Product packaging); B0290 (Numerical analysis) Thesaurus: Electric impedance; Inductance; Integration; Matrix inversion; Network parameters; Packaging; Skin effect; Symmetry Free Terms: 3D partial inductance; Resistance matrix; CPV time; Skin effect; Electrical packaging parameters; Cross-sectional symmetry; Numerical integration; Direct inversion; Partial impedance matrix; Inductance matrices; Uniformly coupled transmission lines; Periodic structure; System matrix Item Availability: CD-ROM. INSPEC 4955589 B9507-0170J-010 C9507-7410D-015 Doc Type: Conference Paper Title: A new three dimensional finite difference time domain (3D-FDTD) simulator for modelling electronic interconnections and packaging Authors: Lu, L.X.; Wu, C.; Litva, J. Affiliation: Commun. Res. Lab., McMaster Univ., Hamilton, Ont., Canada Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.93TH0586-8) p. 92-5 Publisher: IEEE New York, NY, USA Date: 1993 vii+238 pp. Country of Publication: USA ISBN: 0 7803 1427 1 CCC: 0 7803 1427 1/93/$3.00 Language: English Conf. Date: 20-22 Oct. 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc Treatment: Practical; Theoretical/Mathematical Abstract: It has been shown that the finite difference time domain (FDTD) method is an accurate and flexible technique to simulate complex electromagnetic problems. A 3D-FDTD software package is introduced. It can be used to simulate electronic packaging problems from an electromagnetic field point of view. (3 Refs.) Classification: B0170J (Product packaging); B1130B (Computer-aided circuit analysis and design); B2570 (Semiconductor integrated circuits); B2550F (Metallisation and interconnection technology); C7410D (Electronic engineering computing) Thesaurus: Circuit analysis computing; Circuit CAD; Finite difference time-domain analysis; Integrated circuit interconnections; Integrated circuit packaging Free Terms: Electronic interconnections modelling; Three dimensional finite difference time domain simulator; Electronic packaging simulation; Electromagnetic problems; 3D-FDTD software package Item Availability: CD-ROM. INSPEC 4955579 B9507-1320-011 Doc Type: Conference Paper Title: On the extraction of circuit parameters of microstrip elements from MOM-Computed currents Authors: Naishadham, K. Affiliation: Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.93TH0586-8) p. 50-2 Publisher: IEEE New York, NY, USA Date: 1993 vii+238 pp. Country of Publication: USA ISBN: 0 7803 1427 1 CCC: 0 7803 1427 1/93/$3.00 Language: English Conf. Date: 20-22 Oct. 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc Treatment: Theoretical/Mathematical Abstract: Microstrip circuit elements and discontinuities are analyzed by an efficient moment method procedure that utilizes closed-form Green's functions and exploits symmetries to fill the moment matrix efficiently. Reciprocity is applied to derive a new formula for computing the 'voltage' of a point on the microstrip surface, which is used, along with the computed currents, to calculate Z-parameters of the circuit elements. Computed circuit parameters are compared with results obtained independently by the least-squares Prony's method, and with measurements. (6 Refs.) Classification: B1320 (Waveguide components); B1270D (Passive filters and other passive networks); B1130B (Computer-aided circuit analysis and design); B1310 (Waveguides) Thesaurus: Circuit analysis computing; Green's function methods; Least squares approximations; Method of moments; Microstrip circuits; Microstrip discontinuities; Microstrip filters; S-parameters Free Terms: Microstrip circuit elements; S-parameters; Circuit simulation package; Reciprocity; Two-slot microstrip filter; MOM-Computed currents; Discontinuities; Closed-form Green's functions; Moment matrix; Microstrip surface; Z-parameters; Circuit parameters; Least-squares Prony's method Item Availability: CD-ROM. INSPEC 4955575 B9507-0170J-004 C9507-7410D-009 Doc Type: Conference Paper Title: Calculation of multi-port parameters of electronic packages using a general purpose electromagnetics code Authors: Rubin, B.J.; Daijavad, S. Affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA Conf. Title: Electrical Performance of Electronic Packaging (Cat. No.93TH0586-8) p. 37-9 Publisher: IEEE New York, NY, USA Date: 1993 vii+238 pp. Country of Publication: USA ISBN: 0 7803 1427 1 CCC: 0 7803 1427 1/93/$3.00 Language: English Conf. Date: 20-22 Oct. 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE Microwave Theory & Tech. Soc Treatment: Theoretical/Mathematical Abstract: A powerful code developed by the authors to solve radiation and scattering problems from arbitrary 3D dielectric-conductor structures is modified to provide the terminal characteristics of arbitrary package structures. By incorporating a general de-embedding procedure to eliminate end effects, Y- and S-parameters can be obtained for 3D transmission-line structures; other parameters such as the C and L matrices can also be obtained. Results for microstrip twin-tee and mesh-plane structures are presented and compared with results already in the literature. (8 Refs.) Classification: B0170J (Product packaging); B1310 (Waveguides); B5240 (Transmission line theory); B1150F (Distributed linear networks); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing) Thesaurus: Circuit analysis computing; Microstrip lines; Multiport networks; Packaging; S-parameters; Transmission line matrix methods Free Terms: C matrices; Microstrip twin-tee structures; Multiport parameters; Radiation problems Y-parameters; Electronic packages; General purpose electromagnetics code; Scattering problems; Arbitrary 3D dielectric-conductor structures; Terminal characteristics; General de-embedding procedure; End effects; S-parameters; 3D transmission-line structures; L matrices; Mesh-plane structures Item Availability: CD-ROM. INSPEC 4946055 C9506-4230M-037 Doc Type: Conference Paper Title: Scalable architectures with k-ary n-cube cluster-c organization Authors: Basak, D.; Panda, D.K. Affiliation: Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA Conf. Title: Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing (Cat. No.93TH0584-3) p. 780-7 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1993 xviii+823 pp. Country of Publication: USA ISBN: 0 8186 4222 X CCC: 1063-6374/93/$03.00 Language: English Conf. Date: 1-4 Dec. 1993 Conf. Loc: Dallas, TX, USA Conf. Sponsor: IEEE Treatment: Theoretical/Mathematical Abstract: Recent advancements in VLSI and packaging technologies demonstrate attractiveness in building scalable parallel systems using clustered configurations while exploiting communication locality. Clustered architectures using buses or MINs as the inter-cluster interconnection do not satisfy both the above objectives. This paper proposes a new class of k-ary n-cube cluster-c scalable architectures by combining the scalability of k-ary n-cube wormhole-routed networks with the cost-effectiveness of processor cluster designs. This paper focuses on direct cluster interconnection. The interplay between various system parameters and routing schemes are analyzed to determine optimal configurations under the constant bisection bandwidth constraint. Our analysis indicates that small sized clusters with a ring intra-cluster topology and a 2D/3D/4D inter-cluster network connecting these clusters offer best system performance. (15 Refs.) Classification: C4230M (Multiprocessor interconnection); C5220P (Parallel architecture) Thesaurus: Multiprocessor interconnection networks; Parallel architectures Free Terms: Scalable parallel systems; Clustered configurations; Communication locality; Inter-cluster interconnection; K-ary n-cube cluster-c scalable architectures; K-ary n-cube wormhole-routed networks; Processor cluster designs; Direct cluster interconnection; Constant bisection bandwidth constraint Item Availability: CD-ROM. INSPEC 4938869 B9506-2250-013 Doc Type: Conference Paper Title: Impact of low-cost MCM-D on MCM designers' technology choices Authors: Ho, C.W.; Green, H. Affiliation: MicroModule Syst., Inc., Cupertino, CA, USA Conf. Title: Fifteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium (Cat. No.93CH3355-5) p. 481-3 Publisher: IEEE New York, NY, USA Date: 1993 xii+504 pp. Country of Publication: USA ISBN: 0 7803 1424 7 CCC: 0 7803 1424 7/93/$3.00 Language: English Conf. Date: 4-6 Oct. 1993 Conf. Loc: Santa Clara, CA, USA Conf. Sponsor: Electron. Ind. Assoc.; Components, Hybrids & Manuf. Technol. Soc Treatment: General/Review Abstract: Multichip module (MCM)-D has been portrayed as the technology with the most promise, the greatest ability to handle high clock frequencies, and the long-term choice for high-performance applications - although always with a warning that MCM-D was many times more expensive a technology choice than MCM-L. These assumptions are rapidly becoming invalid. MCM-D performance has emerged as foreseen, but at the same time prices for completed modules have fallen greatly. Economics of scale have allowed MCM-D manufacturers to take advantage of their technology by building products that only MCM-D line geometries and form factors make possible. In addition, any enabling technology - like 3-D memory or 3-D stacking of MCM's - for MCM-L will also be usable to equal or greater effect by MCM-D. MCM applications are continuing to follow long-term industry trends for higher performance, lower costs, and smaller form factors. (4 Refs.) Classification: B2250 (Multichip modules); B0170J (Product packaging) Thesaurus: Economics; Integrated circuit design; Integrated circuit interconnections; Integrated circuit manufacture; Integrated circuit packaging; Integrated circuit yield; Multichip modules Free Terms: MCM design; Volume applications; Low-cost MCM-D; Technology choices; Performance; Enabling technology; 3-D memory; 3-D stacking; Smaller form factors Item Availability: CD-ROM. INSPEC 4918595 B9505-0170J-035 Doc Type: Journal Paper Title: Analysis of TAB inner lead fatigue in thermal cycle environments Authors: Cluff, K.D. Affiliation: Air Transp. Syst. Div., Honeywell Inc., Phoenix, AZ, USA Journal: IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A Vol: 18 Iss: 1 p. 101-7 Date: March 1995 Country of Publication: USA ISSN: 1070-9886 CODEN: IMTAEZ CCC: 1070-9886/95/$04.00 Language: English Treatment: Practical; Theoretical/Mathematical Abstract: The inner leads of a Tape Automated Bonding (TAB) device can be subject to early fatigue failures in thermal cycle environments. This paper describes a 3-D nonlinear finite clement analysis of the failure mechanism, and verifies the results by experiment. Some TAB applications require environmental qualification and electrical testing in the unexcised tape carrier or retain a significant portion of the polyimide tape in the assembly. In these cases the Coefficient of Thermal Expansion (CTE) mismatch between the silicon die and polyimide tape can cause plastic strains in the inner leads. Several design variations are quantified. Those with first order effects were found to be encapsulant material, lead length, and lead material. (8 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B0170N (Reliability); B0290T (Finite element analysis) Thesaurus: Encapsulation; Environmental testing; Failure analysis; Fatigue; Finite element analysis; Integrated circuit packaging; Lead bonding; Plastic deformation; Tape automated bonding; Thermal expansion Free Terms: TAB inner lead fatigue; Thermal cycle environments; Fatigue failures; 3D nonlinear finite clement analysis; Failure mechanism; Environmental qualification; Electrical testing; Unexcised tape carrier; Polyimide tape; Coefficient of thermal expansion; CTE mismatch; Plastic strains; Design variations; First order effects; Encapsulant material; Lead length; Lead material Item Availability: CD-ROM. INSPEC 4898227 B9504-1130B-052 C9504-7410D-141 Doc Type: Journal Paper Title: A 3-D electromagnetic simulator for high frequency applications Authors: Jian-X. Zheng Affiliation: Zeland Software Inc., Fremont, CA, USA Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 18 Iss: 1 p. 112-18 Date: Feb. 1995 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/95/$04.00 Language: English Treatment: Application; Practical; Theoretical/Mathematical Abstract: A general purpose full-wave electromagnetic simulator IE3-D has been developed for the analysis and design of high-frequency and high-speed electronic circuit structures. For an arbitrarily shaped 3-D metallic layered structure, the integral equation, and method of moment-based simulator solves the current distribution on the structure expanded into roof-top functions on a set of 3-D triangular and rectangular cells. The circuit parameters are extracted from the solved current distribution in the form of either S-parameters frequency response and RLC-equivalent circuit in SPICE format. (15 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B0290R (Integral equations); B1350 (Microwave circuits and devices); B1265 (Digital electronics); B0170J (Product packaging); C7410D (Electronic engineering computing); C6185 (Simulation techniques); C4180 (Integral equations) Thesaurus: Circuit analysis computing; Current distribution; Digital circuits; Digital simulation; Equivalent circuits; Frequency response; Integral equations; Method of moments; Microwave circuits; Packaging; S-parameters; SPICE Free Terms: 3D electromagnetic simulator; High frequency applications; Full-wave EM simulator; IE3-D; High-speed electronic circuits; Integral equation; Method of moment-based simulator; Current distribution; Roof-top functions; 3D rectangular cells; 3D triangular cells; Circuit parameters; S-parameters frequency response; RLC-equivalent circuit; SPICE format Item Availability: CD-ROM. INSPEC 4898224 B9504-1130B-051 C9504-7410D-140 Doc Type: Journal Paper Title: Algorithms for coupled transient simulation of circuits and complicated 3-D packaging Authors: Silveira, L.M.; Kamon, M.; White, J. Affiliation: Res. Lab. of Electron., MIT, Cambridge, MA, USA Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 18 Iss: 1 p. 92-8 Date: Feb. 1995 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/95/$04.00 Language: English Treatment: Theoretical/Mathematical Abstract: Techniques are described for coupled simulation of complicated 3-D interconnect and nonlinear transistor drivers and receivers. The approach is based on combining: multipole-accelerated method-of-moments techniques for extracting frequency-dependent inductances and resistances for the interconnect; a sectioning method for fitting the frequency-domain data with a rational function; a balanced-realization approach to reducing the order of the rational function in a guaranteed stable manner; and an implementation of fast recursive convolution to incorporate the rational function in SPICE3. Results are presented to demonstrate some of the frequency-dependent effects in a packaging analysis problem. (13 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B0170J (Product packaging); B0290Z (Other numerical methods); C7410D (Electronic engineering computing); C4190 (Other numerical methods) Thesaurus: Circuit analysis computing; Convolution; Distributed parameter networks; Driver circuits; Inductance; Integrated circuit interconnections; Method of moments; Packaging; SPICE; Transient analysis Free Terms: Coupled transient simulation; 3D packaging; Nonlinear transistor drivers; Nonlinear transistor receivers; Multipole-accelerated moment methods; Method-of-moments techniques; Frequency-dependent inductances; Frequency-dependent resistances; Interconnect; Sectioning method; Frequency-domain data; Rational function; Balanced-realization approach; Fast recursive convolution; SPICE3; Packaging analysis problem Item Availability: CD-ROM. INSPEC 4886241 B9504-2570A-007 C9504-7410D-063 Doc Type: Conference Paper Title: Layout-based extraction of IC electrical behavior models Authors: Wang, K.; Rotella, F.; Chen, T.; Yang, D.; Lee, A.; Yu, Z.; Knepper, R.W.; Watt, J.; Dutton, R.W. Affiliation: Center for Integrated Syst., Stanford Univ., CA, USA Conf. Title: International Electron Devices Meeting 1994. Technical Digest (Cat. No.94CH35706) p. 209-12 Publisher: IEEE New York, NY, USA Date: 1994 947 pp. Country of Publication: USA ISBN: 0 7803 2111 1 CCC: 0 7803 2111 1/94/$4.00 Language: English Conf. Date: 11-14 Dec. 1994 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: Electron Devices Soc. IEEE Treatment: Application; Theoretical/Mathematical Abstract: Behavior of IC structures is modeled using a heterogeneous set of tools and derived physical representations. A unified 3D information model is demonstrated with special emphasis on application of solid geometry modeling techniques. Examples used in this presentation include modeling of SRAM technology and interconnect structures that include packaging considerations as well. Issues of mixed level simulations are considered based on circuit and thermal constraints on IC structures. (3 Refs.) Classification: B2570A (Integrated circuit modelling and process simulation); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing) Thesaurus: Circuit analysis computing; Circuit CAD; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit modelling; Integrated circuit packaging; SRAM chips Free Terms: Layout-based extraction; IC electrical behavior models; Unified 3D information model; Solid geometry modeling techniques; SRAM technology; Interconnect structures; Packaging considerations; Mixed level simulations Item Availability: CD-ROM. INSPEC 4874636 B9503-0170J-062 C9503-7410D-107 Doc Type: Conference Paper Title: Algorithms for coupled transient simulation of circuits and complicated 3-D packaging Authors: Silveira, L.M.; Kamon, M.; White, J. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Conf. Title: 1994 Proceedings. 44th Electronic Components and Technology Conference (Cat. No.94CH3241-7) p. 962-70 Publisher: IEEE New York, NY, USA Date: 1994 xvii+1118 pp. Country of Publication: USA ISBN: 0 7803 0914 6 CCC: 0569-5503/94/0000-0962$3.00 Language: English Conf. Date: 1-4 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol. Soc.; Electron. Ind. Assoc Treatment: Theoretical/Mathematical Abstract: In this paper techniques are described for coupled simulation of complicated 3-D interconnect and nonlinear transistor drivers and receivers. The approach is based on combining: multipole-accelerated method-of-moments techniques for extracting frequency-dependent inductances and resistances for the interconnect; a sectioning method for fitting the frequency-domain data with a rational function; a balanced-realization approach to reducing the order of the rational function in a guaranteed stable manner; and an implementation of fast recursive convolution to incorporate the rational function in SPICE3. Results are presented to demonstrate some of the frequency-dependent effects in a packaging analysis problem. (13 Refs.) Classification: B0170J (Product packaging); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing) Thesaurus: Circuit analysis computing; Digital simulation; Driver circuits; Method of moments; Packaging; SPICE; Transient analysis Free Terms: Coupled transient simulation; 3D packaging; 3D interconnect; Nonlinear transistor drivers; Nonlinear transistor receivers; Multipole-accelerated moment method; Frequency-dependent inductances; Frequency-dependent resistances; Sectioning method; Frequency-domain data; Rational function; Balanced-realization approach; Fast recursive convolution; SPICE3; Packaging analysis problem; Frequency-dependent effects Item Availability: CD-ROM. INSPEC 4874605 B9503-0170J-051 Doc Type: Conference Paper Title: Impact of moisture/reflow induced delaminations on integrated circuit thermal performance Authors: Conrad, T.R.; Shook, R.L. Affiliation: AT&T Bell Labs., Allentown, PA, USA Conf. Title: 1994 Proceedings. 44th Electronic Components and Technology Conference (Cat. No.94CH3241-7) p. 527-31 Publisher: IEEE New York, NY, USA Date: 1994 xvii+1118 pp. Country of Publication: USA ISBN: 0 7803 0914 6 CCC: 0569-5503/94/0000-0527$3.00 Language: English Conf. Date: 1-4 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol. Soc.; Electron. Ind. Assoc Treatment: Practical; Theoretical/Mathematical; Experimental Abstract: Ambient moisture uptake in plastic surface mount IC packages can cause delamination of critical internal surfaces within the package during reflow assembly. Delaminations can result in reduced thermal cycling life performance or provide for a pathway for the ingress of chemicals and contaminates. The effects that moisture/reflow induced delaminations can have on the thermal performance of plastic packaged ICs are not entirely understood. In this paper, the thermal performance of moisture/reflow delaminated ICs is reported. The effective sensitivity of the thermal performance as a result of the moisture/reflow induced delaminations was measured by experimental thermal resistance measurements ( theta /sub JA/) and compared to theoretical calculations based on Finite Element Analysis (FEA). Both 3-D and 2-D FEA models were developed for predictive responses which gave excellent correlation to the experimental measurements. The results showed that interfacial delaminations can cause a measurable increase in theta /sub JA/. The magnitude of the increase is found to be proportional to the power consumption of the device and dependent on the delamination gap thickness. Expected reliability degradation as a result of die temperature rise from the interfacial delaminations is most significant for plastic packaged devices of power ratings greater than about 1 W. (15 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B0170N (Reliability); B0290T (Finite element analysis) Thesaurus: Delamination; Finite element analysis; Integrated circuit packaging; Integrated circuit reliability; Life testing; Microassembling; Moisture; Plastic packaging; Reflow soldering; Surface mount technology; Thermal resistance Free Terms: Moisture/reflow induced delaminations; Integrated circuit thermal performance; Ambient moisture uptake; Plastic surface mount IC packages; Critical internal surfaces; Reflow assembly; Thermal cycling life performance; Thermal resistance measurements; Finite element analysis; Predictive responses; Power consumption; Delamination gap thickness; Reliability degradation; Die temperature rise; Power ratings Item Availability: CD-ROM. INSPEC 4868835 B9503-5230-021 Doc Type: Conference Paper Title: Heatsink radiation as a function of geometry Authors: Brench, C.E. Affiliation: Digital Equipment Corp., Maynard, MA, USA Conf. Title: Chicago 1994. Compatibility in the Loop. IEEE International Symposium on EMC. Symposium Record (Cat. No.94CH3347-2) p. 105-9 Publisher: IEEE New York, NY, USA Date: 1994 xi+514 pp. Country of Publication: USA ISBN: 0 7803 1398 4 CCC: 0 7803 1398 4/94/0000-0018$4.00 Language: English Conf. Date: 22-26 Aug. 1994 Conf. Loc: Chicago, IL, USA Treatment: Practical; Experimental Abstract: In today's high performance computers the need to cool the CPU and other VLSI devices with attached heatsinks is very common. The heatsink geometry is usually driven by the thermal requirements in conjunction with the device packaging needs. As the processor speeds increase the die power dissipation also increases, leading to an increase in the preferred heatsink size. In this paper the variations in the radiation characteristics of heatsinks are examined with respect to their geometries by use of a three dimensional finite difference time domain (FDTD) technique. (3 Refs.) Classification: B5230 (Electromagnetic compatibility and interference); B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B0290Z (Other numerical methods) Thesaurus: Electromagnetic interference; Finite difference time-domain analysis; Heat sinks; Packaging; VLSI Free Terms: High performance computers; CPU; VLSI devices; Heatsink geometry; Processor speeds; Thermal requirements; Packaging; Die power dissipation; Heatsink size; Heatsink radiation characteristics; Finite difference time domain; 3D FDTD Item Availability: CD-ROM. INSPEC 4858568 B9502-0170J-030 Doc Type: Conference Paper Title: Compliant bumps for adhesive flip chip assembly Authors: Keswick, K.; German, R.; Breen, M.; Nolan, R. Affiliation: MCC, Austin, TX, USA Conf. Title: 1994 Proceedings. 44th Electronic Components and Technology Conference (Cat. No.94CH3241-7) p. 7-15 Publisher: IEEE New York, NY, USA Date: 1994 xvii+1118 pp. Country of Publication: USA ISBN: 0 7803 0914 6 CCC: 0569-5503/94/0000-0007$3.00 Language: English Conf. Date: 1-4 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol. Soc.; Electron. Ind. Assoc Treatment: Practical; Experimental Abstract: Flip-chip-on-glass (FCOG) is susceptible to electrical opens for a variety of reasons including, but not limited to, movement in the z-axis caused by flip chip adhesive CTE and water absorption of the adhesive. Flip chip assembly to cofired ceramic and laminate substrates suffers from these problems as well as others, such as bow or twist in the substrate and bond pad height irregularities. Success with adhesive flip chip connections to these substrates has, to date, been limited. Commercially available adhesives have either failed to produce reliable bonds, or have suffered from long cure time or a lack of reworkability. A solution to these problems has been demonstrated by forming compliant bumps on the chip or substrate bond pads using a photoimagible polymer coated with a thin layer of gold. Bumps 17 mu m tall with diameters between 17 mu m and 95 mu m have been fabricated and bonded. The resulting compliant bump structure provides 30% of the bump height (5 mu m) within the elastic compression range. This compliance eliminates many of the demands placed on the assembly adhesives by other electrical contacting methods (such as solid metal bumps or particles). Compliant bumps allow the use of commercially available, fast curing, easily reworkable adhesives for reliable flip chip assembly. (0 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B0170N (Reliability) Thesaurus: Adhesion; Flip-chip devices; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit reliability; Lead bonding Free Terms: Compliant bumps; Adhesive flip chip assembly; Flip-chip-on-glass; Electrical opens; Flip chip adhesive CTE; Water absorption; Ceramic substrates; Laminate substrates; Bond pad height irregularities; Bow; Twist; Photoimagible polymer; Elastic compression range; Curing; Reworkable adhesives; 17 To 95 micron Numerical Index: Size 1.7E-05 to 9.5E-05 m Item Availability: CD-ROM. INSPEC 4857591 C9502-1290-030 Doc Type: Conference Paper Title: Hybrid genetic algorithm for container packing in three dimensions Authors: Lin, J.-L.; Foote, B.; Pulat, S.; Chang, C.-H.; Cheung, J.Y. Affiliation: Oklahoma Univ., USA Conf. Title: Proceedings. The Ninth Conference on Artificial Intelligence for Applications (Cat. No.93CH3254-0) p. 353-9 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1993 xvi+471 pp. Country of Publication: USA ISBN: 0 8186 3840 0 CCC: 1043-0989/93/$03.00 Language: English Conf. Date: 1-5 March 1993 Conf. Loc: Orlando, FL, USA Conf. Sponsor: IEEE Comput. Soc. Tech. Committee on Pattern Analysis & Mach. Intelligence; AAAI; Canadian Soc. Comput. Stud. Intelligence Treatment: Theoretical/Mathematical Abstract: The concept of genetics using multiple-chromosomes is applied to a 3D container packing problem. The 3D packing problem deals with packing a given set of regular shaped boxes of different sizes and weights into larger containers. The algorithm must seek to minimize the wasted space under a constraint: the heavier and the larger boxes must be placed below the lighter ones. The present emphasis is to find a good solution quickly by heuristic means. A set of heuristic rules is incorporated into the genetic algorithm (GA) approach to aid in optimization. This hybrid GA yields an optimization algorithm that outperforms either of the parts. The simulation results showed that the new algorithm has better adaptivity for large problems and near optimal solutions for small problems. (40 Refs.) Classification: C1290 (Applications of systems theory); C1180 (Optimisation techniques); C1230 (Artificial intelligence) Thesaurus: Genetic algorithms; Heuristic programming; Operations research; Packaging Free Terms: Hybrid genetic algorithm; Box size; Box weight; Wasted space minimization; Multiple-chromosomes; 3D container packing problem; Regular shaped boxes; Heuristic rules; Optimization algorithm; Simulation; Adaptivity; Near optimal solutions Item Availability: CD-ROM. INSPEC 4854347 B9502-1350H-011 Doc Type: Journal Paper Title: A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module Authors: Shibata, T.; Kimura, S.; Kimura, H.; Imai, Y.; Umeda, Y.; Akazawa, Y. Affiliation: NTT LSI Labs., Kanagawa, Japan Journal: IEEE Journal of Solid-State Circuits Vol: 29 Iss: 12 p. 1537-44 Date: Dec. 1994 Country of Publication: USA ISSN: 0018-9200 CODEN: IJSCBC CCC: 0018-9200/94/$04.00 Language: English Treatment: Practical Abstract: A DC-60 GHz, 9 dB distributed amplifier IC module is fabricated with 0.15 mu m InAlAs-InGaAs low-noise HEMTs with 155 GHz f/sub T/ and 234 GHz f/sub max/. The device is mounted in a metal package with 1.8 mm coaxial cable signal interfaces. The package is specially designed using three-dimensional electromagnetic field analyses, resulting in very flat frequency characteristics of the module within 1.5 dB gain ripples over the entire bandwidth. A multichip module loaded with two amplifier ICs in cascade is also fabricated, and operates at a 17.5 dB gain from 60 kHz to 48 GHz. The 1 dB gain compression output power is about 5 dBm for both modules. The noise figure of the single-chip module is approximately 4 dB over a 10-40 GHz frequency range. (7 Refs.) Classification: B1350H (Microwave integrated circuits); B1220 (Amplifiers); B2570H (Other field effect integrated circuits); B2250 (Multichip modules); B0170J (Product packaging) Thesaurus: Coplanar waveguides; Distributed amplifiers; Field effect MIMIC; HEMT integrated circuits; Integrated circuit packaging; Millimetre wave amplifiers; Multichip modules; Wideband amplifiers Free Terms: Design technique; Distributed baseband amplifier; Amplifier IC module; Low-noise HEMTs; Metal package; Coaxial cable signal interfaces; Three-dimensional EM field analyses; 3D electromagnetic field analyses; Multichip module; Cascaded amplifiers; Single-chip module; MCM; MIMIC; MM-wave IC; 60 GHz; 0 To 60 GHz; 0.15 Micron; 9 DB; 17.5 DB; 4 DB; InAlAs-InGaAs Numerical Index: Bandwidth 6.0E+10 Hz; Frequency 0.0E+00 to 6.0E+10 Hz; Size 1.5E-07 m; Gain 9.0E+00 dB; Gain 1.75E+01 dB; Noise figure 4.0E+00 dB Chemical Index: InAlAs-InGaAs/int InAlAs/int InGaAs/int Al/int As/int Ga/int In/int InAlAs/ss InGaAs/ss Al/ss As/ss Ga/ss In/ss Item Availability: CD-ROM. INSPEC 4852710 B9502-7630-039 C9502-7460-041 Doc Type: Conference Paper Title: High-performance, AMLCD-based 'smart' display for the Space Shuttle glass cockpit Authors: Thomsen, S.V.; Hancock, W.R. Affiliation: Satellite Syst. Oper., Honeywell Inc., Glendale, AZ, USA Conf. Title: AIAA/IEEE Digital Avionics Systems Conference. 13th DASC (Cat. No.94CH3573-0) p. 281-8 Publisher: IEEE New York, NY, USA Date: 1994 639 pp. Country of Publication: USA ISBN: 0 7803 2425 0 CCC: 0 7803 2425 0/94/$4.00 Language: English Conf. Date: 30 Oct.-3 Nov. 1994 Conf. Loc: Phoenix, AZ, USA Treatment: Practical Abstract: A production program is underway for an Active Matrix Liquid Crystal Display (AMLCD) for the National Aeronautics and Space Administration (NASA) Space Shuttle glass cockpit upgrade. A 'smart' display architecture is used with a powerful Reduced Instruction Set Computer (RISC) processing element and custom graphics accelerator that can render two- and three-dimensional (2-D and 3-D), fully anti-aliased graphical images at 30 Hz update rates. In addition, the Multifunction Display Unit (MDU) can display external NTSC/RS-170 video to crew members, or output an NTSC signal for repeater monitor requirements. The unit is a very compact design-minimizing volume, weight, and power. Advanced AMLCD technology delivers exceptional brightness, gray-scale performance, off-axis viewing, and dynamic image response across the full 6.71*6.71 in. active display area. High resolution is achieved with 1152*1152 color dots and 28 shades of gray per primary color. Exceptional imaging quality, throughput, graphics generation, and reliability all combine to produce a display package that greatly enhances flight-deck performance. (3 Refs.) Classification: B7630 (Avionic systems and aerospace instrumentation); B4150D (Liquid crystal devices); B7260 (Display technology and systems); C7460 (Aerospace engineering computing); C5220 (Computer architecture) Thesaurus: Aerospace computing; Computer architecture; Liquid crystal displays; Reduced instruction set computing; Space vehicle electronics; Special purpose computers Free Terms: Smart display; Space Shuttle glass cockpit; Production program; Active matrix liquid crystal display; Packaging; NASA; Reduced Instruction Set Computer; RISC; Custom graphics accelerator; Antialiased graphical images; Multifunction Display Unit; NTSC/RS-170; Design-minimizing volume; Brightness; Gray-scale performance; Off-axis viewing; Dynamic image response; Active display area; Color dots; Imaging quality; Throughput; Graphics generation Item Availability: CD-ROM. INSPEC 4846877 B9502-0170J-005 C9502-7410D-031 Doc Type: Conference Paper Title: Efficient three-dimensional LCR extraction and modeling of VLSI packages Authors: Specks, J.W. Affiliation: Microcontroller Design Center, Motorola Inc., Munich, Germany Conf. Title: Proceedings of the 36th Midwest Symposium on Circuits and Systems (Cat. No.93CH3381-1) p. 1166-9 vol.2 Publisher: IEEE New York, NY, USA Date: 1993 2 vol. xxxv+1565 pp. Country of Publication: USA ISBN: 0 7803 1760 2 CCC: CH3381-1/93/$01.00 Language: English Conf. Date: 16-18 Aug. 1993 Conf. Loc: Detroit, MI, USA Conf. Sponsor: Wayne State Univ.; IEEE Circuits & Syst. Soc Treatment: Practical; Theoretical/Mathematical Abstract: The computational cost of 3-D LCR package modeling is reduced by several techniques. Capacitance extraction uses a novel potential-adapted grid and an iterative equation solver. Inductance calculation is based on a mixed analytical/numerical integration method and a geometry dependent filament approximation. The resulting circuit model automatically takes into account only significant LC couplings. (8 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B0290F (Interpolation and function approximation); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing); C4130 (Interpolation and function approximation) Thesaurus: Circuit analysis computing; Computational complexity; Crosstalk; Integrated circuit interconnections; Integrated circuit packaging; Iterative methods; VLSI Free Terms: Three-dimensional LCR extraction; VLSI packages; Computational cost; Capacitance extraction; Potential-adapted grid; Iterative equation solver; Inductance calculation; Mixed analytical/numerical integration method; Geometry dependent filament approximation; Circuit model; LC couplings; Circuit simulation; Crosstalk; Multiconductor systems Item Availability: CD-ROM. INSPEC 4838656 B9501-4180-014 C9501-5270-012 Doc Type: Journal Paper Title: Optoelectronic integrated systems based on free-space interconnects with an arbitrary degree of space variance Authors: Drabik, T.J. Affiliation: Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA Journal: Proceedings of the IEEE Vol: 82 Iss: 11 p. 1595-622 Date: Nov. 1994 Country of Publication: USA ISSN: 0018-9219 CODEN: IEEPAD CCC: 0018-9219/94/$04.00 Language: English Treatment: Theoretical/Mathematical; Experimental Abstract: It is appealing to contemplate how VLSI or wafer-scale integrated systems incorporating free-space optical interconnection might outperform purely electrically interconnected systems. This paper first provides a uniform treatment of a general class of optical interconnects based on a Fourier-plane imaging system with an array of sources in the object plane and an array of receptors in the image plane. Sources correspond to data outputs of processing 'cells,' and receptors to their data inputs. A general abstract optical imaging model, capable of representing a large class of real systems, is analyzed to yield constructive upper bounds on system volume that are comparable to those arising from '3-D VLSI' computational models. These bounds, coupled with technologically derived constraints, form the heart of a design methodology for optoelectronic systems that uses electronic and optical elements each to their greatest advantage, and exploits the available spatial volume and power in the most efficient way. Many of these concepts are embodied in a demonstration project that seeks to implement a bit-serial, multiprocessing system with a radix-2 butterfly topology, and incorporates various new technology developments. (130 Refs.) Classification: B4180 (Optical logic devices and optical computing techniques); B2550F (Metallisation and interconnection technology); B4270 (Integrated optoelectronics); B0170J (Product packaging); C5270 (Optical computing techniques); C4230M (Multiprocessor interconnection); C5220P (Parallel architecture); C5440 (Multiprocessing systems) Thesaurus: Hypercube networks; Integrated circuit packaging; Integrated optoelectronics; Interconnected systems; Optical computing; Optical interconnections; VLSI Free Terms: Optoelectronic integrated systems; Free-space interconnects; Space variance; VLSI; Wafer-scale integrated systems; Free-space optical interconnection; Fourier-plane imaging system; Object plane; Image plane; Data outputs; Data inputs; Abstract optical imaging model; Real systems; Constructive upper bounds; Design methodology; Optoelectronic systems; Optical elements; Spatial volume; Bit-serial multiprocessing system; Radix-2; Butterfly topology Item Availability: CD-ROM. INSPEC 4828921 B9501-2250-004 Doc Type: Conference Paper Title: Enhanced MCM-C package performance by formation of improved 3-D interconnections Authors: Sarfaraz, M.A.; Tong, C.; Yau, Y.-W. Affiliation: IBM Corp., Hopewell Junction, NY, USA Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 1067-71 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-1067$03.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Practical; Experimental Abstract: The authors introduce an improved 3-D interconnection fabricating technology which uses an electron beam to generate surface trenches in green ceramic sheets for the interconnection wirings. The electron beam is capable of generating narrow lines as well as high-density wiring patterns. Electron-beam-formed line cross-sections (line width and thickness) can be adjusted for electrical performance optimization. CMOS and ECL (emitter coupled logic) drivers require different optimized transmission line characteristics for high-performance digital systems. It is shown how the interconnection's cross-sectional dimensions can be controlled by electron-beam machining. Computer simulation results on the range of electrical characteristics achievable in these interconnects as the line space and line cross-section are varied are shown. (10 Refs.) Classification: B2250 (Multichip modules); B0170J (Product packaging); B2220G (Thick film circuits) Thesaurus: Electron beam machining; Integrated circuit interconnections; Multichip modules; Thick film circuits Free Terms: MCM-C package performance; 3D interconnection fabrication technology; Electron-beam machining; Surface trenches; Green ceramic sheets; Interconnection wirings; High-density wiring patterns; Electrical performance optimization; CMOS drivers; ECL drivers; Optimized transmission line characteristics; High-performance digital systems; Interconnection cross-sectional dimensions; Computer simulation; Line width Item Availability: CD-ROM. INSPEC 4828908 B9501-0170J-008 C9501-5490-002 Doc Type: Conference Paper Title: SS-1 supercomputer cooling system Authors: Ing, P.; Sperry, C.; Philstrom, R.; Claybaker, P.; Webster, J.; Cree, R. Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 218-37 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0218$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Application; Practical Abstract: To achieve the speeds required of the SS-1 supercomputer, a high power ECL chip set was developed for the CPU. The 0.65 cm/sup 2/ chip has an absolute maximum power of 40 watts, translating to a chip level heat flux of 95 W/cm/sup 2/. To achieve minimum signal line length, a compact 3D packaging configuration is required. Board pitch in a 3D module is 2.1 cm for the double-sided CPU and 1.96 cm for the double-sided memory. The corresponding board level heat flux is 15.4 W/cm/sup 2/ and the 3D power density is 3.24 W/cm/sup 3/. The SS-1 mainframe dissipates 61 KW with an additional 11.5 KW dissipated in the I/O concentrator. Heat must be removed at a high enough rate to maintain chip temperatures at 65 degrees C average and 82 degrees C maximum to ensure reliability and functionality. This paper describes how SSI meet this challenge by a novel liquid impingement cooling methodology. (6 Refs.) Classification: B0170J (Product packaging); B8560 (Refrigeration and cold storage); C5490 (Other aspects of analogue and digital computers); C5420 (Mainframes and minicomputers) Thesaurus: Cooling; Mainframes; Multichip modules; Packaging; Refrigeration Free Terms: SS-1 supercomputer; Cooling system; High power ECL chip set; Chip level heat flux; Minimum signal line length; 3D packaging configuration; Board pitch; Double-sided CPU; 3D power density; SS-1 mainframe; I/O concentrator; Chip temperatures; Liquid impingement cooling; 40 W; 2.1 Cm; 1.96 Cm; 61 KW; 11.5 KW; 65 DegC; 82 DegC Numerical Index: Power 4.0E+01 W; Size 2.1E-02 m; Size 1.96E-02 m; Power 6.1E+04 W; Power 1.15E+04 W; Temperature 3.38E+02 K; Temperature 3.55E+02 K Item Availability: CD-ROM. INSPEC 4828907 B9501-0170J-007 Doc Type: Conference Paper Title: Accelerated life test of z-axis conductive adhesives Authors: Chang, D.D.; Fulton, J.A.; Ling, H.C.; Schmidt, M.B.; Sinitski, R.E.; Wong, C.P. Affiliation: Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 211-17 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0211$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Application; Practical; Experimental Abstract: Conductive-particles filled adhesives have been widely used for flex-to-rigid board interconnections in many consumer electronics applications, such as calculators and palmcorders. Most of the applications were in coarse pitch interconnections where the adjacent conductor's distance is greater than 10 mil. The success of coarse pitch applications has increased the interest to use such adhesives in fine pitch applications, such as flip-chip on board interconnection. Since these materials contain metallic particles to conduct currents in the z-direction (i.e. perpendicular to the plane of circuit board), their propensity for metal migration is a concern. Therefore we have applied accelerated temperature, humidity and bias (THB) tests to a group of materials designed for fine pitch applications. Our studies include two phases. Phase-I focused on the high voltage (100 V) THB test and the associated conduction and failure mechanisms. Phase-II evaluates the time-to-fail under medium (50 V) and low voltage (10 V) THB conditions. The results of Phase-I studies showed significant metal migration in our tests, and we proposed enhanced electric field stresses (10/sup 4/ to 10/sup 5/ V/cm) as the driving force for failures. (6 Refs.) Classification: B0170J (Product packaging); B0170E (Production facilities and engineering); B2240 (Microassembly techniques); B0170N (Reliability); B0550 (Composite materials (engineering materials science)) Thesaurus: Adhesion; Consumer electronics; Failure analysis; Fine-pitch technology; Flexible structures; Flip-chip devices; Integrated circuit packaging; Life testing; Particle reinforced composites Free Terms: Accelerated life test; Z-axis conductive adhesives; Conductive-particles filled adhesives; Consumer electronics; Fine pitch applications; Flip-chip on board interconnection; Metal migration; Failure mechanisms; Time-to-fail evaluation; Electric field stresses; 10 To 100 V Numerical Index: Voltage 1.0E+01 to 1.0E+02 V Item Availability: CD-ROM. INSPEC 4823770 B9412-0170J-123 C9412-5490-009 Doc Type: Conference Paper Title: Spray cooling for the 3-D cube computer Authors: Tilton, D.E.; Tilton, C.L.; Moore, C.J.; Ackerman, R.E. Affiliation: Isothermal Syst. Res. Inc., Colton, WA, USA Conf. Title: InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM IV. THEME: 'Concurrent Engineering and Thermal Phenomena' (Cat. No.94CH3340-7) p. 169-76 Publisher: IEEE New York, NY, USA Date: 1994 xi+292 pp. Country of Publication: USA ISBN: 0 7803 1372 0 CCC: 0 7803 1372 0/94/$3.00 Language: English Conf. Date: 4-7 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: K-16 on Heat Transfer in Electron. Equipment, Heat Transfer Div., ASME; Electron. Packaging Div. ASME; Components, Packaging & Manuf. Technol. IEEE; Int. Soc. Hybrid Microelectron.; NIST Treatment: Application; Practical; Experimental Abstract: The results of an experimental investigation into high performance thermal management for an advanced 3-D computer are presented. Chips are mounted on synthetic diamond substrates. The substrates are then stacked and integrated with vertical vias. Two faces of the resulting 'cube' computer are reserved for clamping the structure together, two are reserved for power insertion and signal I/O, and the remaining two faces are spray cooled. The heat generated by the chips is conducted laterally out to the cube faces in the high thermal conductivity diamond substrates. The edges of the substrates protrude through a seal plate into a compact spray chamber. Miniature atomizers are used to spray a dielectric coolant onto the substrate edges where the coolant vaporizes to carry away the waste heat. The vapor is condensed in an ambient heat exchanger and the liquid is recycled in a closed-loop system. Experimental results are presented for two different spray plate configurations using a stack of copper heater plates to simulate one half of the computer. Finite element analysis is used to aid in interpretation of the results and predict the junction temperatures that would result from a given spray plate configuration, computer geometry, and chip power loading. The results indicate that very high volume density heat removal is possible (15-20 kW from a four inch cube). Thus, the 3-D computer concept may be suitable for very high performance computing. (2 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis); C5490 (Other aspects of analogue and digital computers); C4185 (Finite element analysis); C5440 (Multiprocessing systems) Thesaurus: Cooling; Finite element analysis; Packaging Free Terms: Spray cooling; 3D cube computer; Thermal management; Synthetic diamond substrates; Vertical vias; Compact spray chamber; Dielectric coolant; Ambient heat exchanger; Closed-loop system; Copper heater plates; Finite element analysis; Junction temperatures; Computer geometry; Chip power loading; Heat removal; 15 To 20 kW; 4 In Numerical Index: Power 1.5E+04 to 2.0E+04 W; Size 1.0E-01 m Item Availability: CD-ROM. INSPEC 4823761 B9412-0170J-117 Doc Type: Conference Paper Title: Modelling of thermal vias in thin film multichip modules Authors: Christiaens, F.; Beyne, E.; Berghmans, J. Affiliation: IMEC, Heverlee, Belgium Conf. Title: InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM IV. THEME: 'Concurrent Engineering and Thermal Phenomena' (Cat. No.94CH3340-7) p. 101-7 Publisher: IEEE New York, NY, USA Date: 1994 xi+292 pp. Country of Publication: USA ISBN: 0 7803 1372 0 CCC: 0 7803 1372 0/94/$3.00 Language: English Conf. Date: 4-7 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: K-16 on Heat Transfer in Electron. Equipment, Heat Transfer Div., ASME; Electron. Packaging Div. ASME; Components, Packaging & Manuf. Technol. IEEE; Int. Soc. Hybrid Microelectron.; NIST Treatment: Theoretical/Mathematical Abstract: A semi-analytical model is presented for evaluating the thermal resistance of via networks used in thin film multichip modules. Correlations between dimensionless groups were derived from numerical data. Therefore, the via network was divided in three basic elements. This allows one to reconstruct the network as a series and parallel connection. The results of this semi-analytical model are compared with those of an existing analytical model and a 3D finite element model. Good agreement between the three models was obtained. The heat conduction efficiency of a staggered thermal via network is defined and the influence of several parameters was investigated. (6 Refs.) Classification: B0170J (Product packaging); B2220E (Thin film circuits) Thesaurus: Modelling; Multichip modules; Thermal analysis; Thermal resistance; Thin film circuits Free Terms: Thermal vias; Thin film multichip modules; Semi-analytical model; Thermal resistance; Via networks; Heat conduction efficiency; Staggered thermal via network; MCM; Modelling Item Availability: CD-ROM. INSPEC 4823756 B9412-2210B-018 Doc Type: Conference Paper Title: Thermal design rules for electronic components on conducting boards in passively cooled enclosures Authors: Lall, B.S.; Ortega, A.; Kabir, H. Affiliation: Dept. of Aerosp. & Mech. Eng., Arizona Univ., Tucson, AZ, USA Conf. Title: InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM IV. THEME: 'Concurrent Engineering and Thermal Phenomena' (Cat. No.94CH3340-7) p. 50-61 Publisher: IEEE New York, NY, USA Date: 1994 xi+292 pp. Country of Publication: USA ISBN: 0 7803 1372 0 CCC: 0 7803 1372 0/94/$3.00 Language: English Conf. Date: 4-7 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: K-16 on Heat Transfer in Electron. Equipment, Heat Transfer Div., ASME; Electron. Packaging Div. ASME; Components, Packaging & Manuf. Technol. IEEE; Int. Soc. Hybrid Microelectron.; NIST Treatment: Practical Abstract: A better understanding is needed of the approaches and limitations for rejecting heat dissipated from VLSI components mounted on multi-layer printed circuit boards housed in small enclosures, as for example those encountered in small consumer electronics, and, in notebook, laptop, or hand-held personal computers. This paper derives new first order thermal design formulae for determining the peak temperatures of sources on conducting substrates, and for determining the thermal 'zone of influence' or 'footprint' associated with a component on a board. A one-dimensional thin board radial fin approach is used with inclusion of a circular source to represent the heat dissipating component. Exact solutions are presented for sources at the center, edge, and corner of a rectangular board. The results are compared with with both 2-d and 3-d calculations for rectangular sources on a board using the finite element method. Excellent agreement is found in predicting the maximum temperature, with maximum differences of order 10%. Simple algebraic design formulae, useful for rapid estimation, are derived from the complete solutions by taking advantage of the asymptotic behavior at small and large values of the board parameter, m. An unambiguous thermal footprint radius is defined in terms of the tangent line at the inflection point of the temperature profile. Parametric studies show that the radius corresponds to the point at which the board temperature drops to roughly 18% of its peak temperature, for all variations of board thickness and conductivity of practical interest. The simple analytical model is used to predict the temperatures on a populated board, using a linear superposition principle, and it is found to be in good agreement with experimental results for boards with multiple heat sources. (23 Refs.) Classification: B2210B (Printed circuit layout and design); B0290T (Finite element analysis); B0170J (Product packaging) Thesaurus: Cooling; Finite element analysis; Packaging; Printed circuit design Free Terms: Thermal design rules; Electronic components; Conducting boards; Passively cooled enclosures; VLSI components; Multi-layer printed circuit boards; One-dimensional thin board radial fin; Rectangular board; Finite element method; Maximum temperature; Asymptotic behavior; Thermal footprint radius; Board temperature; Linear superposition principle Item Availability: CD-ROM. INSPEC 4823455 B9412-0170J-077 Doc Type: Conference Paper Title: High-frequency inductance measurements and characterization of alloy 42 and copper packages Authors: Chi-Taou Tsai; Osorio, R.; Wai-Yeung Yip; Sparkman, A.; Sharma, R.; Astrain, H. Affiliation: Motorola Inc., Chandler, AZ, USA Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 635-40 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0635$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Theoretical/Mathematical; Experimental Abstract: A network analysis based high-frequency inductance technique was used to measure the package inductance of various A42 and Cu QFP packages. A continuous frequency range of 2.6 MHz to >500 MHz corresponding to the relevant speed/bandwidth of today's ICs was employed. Results indicated that while the inductance of all the Cu packages were essentially constant across the frequency band, the inductance of A42 packages varied appreciably with the frequency. The inductance of a typical A42 package was three times that of a Cu package at 2.6 MHz but decreased to only 10%-20% higher than that of a Cu package above 250 MHz. The lead resistance of A42 also increased sharply with increasing frequency and could become an important factor in determining the electrical performance. Based upon the preliminary analyses, the frequency-dependent inductance and resistance of A42 packages were attributed to the interaction between the skin effect and the non-unity permeability of ferromagnetic materials. To verify the theory and to test possible electrical enhancement for the A42, different surface-treated packages, including an Au-plated A42, a Pd/Ni-plated A42 and a Pd/Ni-plated Cu CQFP packages were characterized for their inductance and resistance. A 3-D field solver was also used to derive the permeability of the A42 materials at different frequencies. To further study the impact on high-speed digital chips where signals are usually analyzed in the time domain, a test structure made of both A42 traces and Cu traces was characterized using a time domain reflectometer for impedance, delay, and crosstalk. Both the frequency-domain and the time-domain results for A42 and Cu packages are summarized in this paper and their implications discussed. (5 Refs.) Classification: B0170J (Product packaging); B7310J (Impedance and admittance measurement) Thesaurus: Copper; Crosstalk; Delays; Inductance; Inductance measurement; Iron alloys; Magnetic permeability; Packaging; Skin effect; Time-domain analysis Free Terms: High-frequency inductance technique; HF inductance measurements; Characterization; Alloy 42 packages; Cu packages; Network analysis; QFP packages; IC packages; Lead resistance; Skin effect; Nonunity permeability; Ferromagnetic materials; Surface-treated packages; Au-plated A42; Pd/Ni-plated A42; Pd/Ni-plated Cu; 3D field solver; High-speed digital chips; Time domain analysis; Crosstalk; Delay; 2.6 To 500 MHz; PdNi-Cu Numerical Index: Frequency 2.6E+06 to 5.0E+08 Hz Chemical Index: PdNi-Cu/int PdNi/int Cu/int Ni/int Pd/int PdNi/bin Ni/bin Pd/bin Cu/el; PdNi/int Fe/int Ni/int Pd/int PdNi/bin Fe/bin Ni/bin Pd/bin Item Availability: CD-ROM. INSPEC 4823454 B9412-0170J-076 C9412-7410D-205 Doc Type: Conference Paper Title: Highly optimized and robust calculation of signal propagation parameters in electronic packages Authors: Efrat, I.; Tismenetsky, M.; Webman, I.; Rubin, B. Affiliation: IBM Sci. & Technol., Haifa, Israel Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 630-4 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0630$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Theoretical/Mathematical Abstract: A powerful technique is described for optimizing electromagnetic codes that provide the signal propagation characteristics of package structures. The technique is specifically adapted to an algorithm, already described in the literature, and replaces the standard determinant search and linear equation solution subroutines. Through mechanical speed-up and improved numerical convergence, the run time for large cases is reduced by an order of magnitude. This speed-up makes it practical to solve realistic 3D problems on typical workstations. Details of this technique, along with other optimizations in the algorithm, are presented. Numerous cases involving practical package structures are analyzed, with focus placed on the differences in run time and convergence between the new and standard techniques. (5 Refs.) Classification: B0170J (Product packaging); B0260 (Optimisation techniques); B1130B (Computer-aided circuit analysis and design); B0290Z (Other numerical methods); C7410D (Electronic engineering computing); C1180 (Optimisation techniques); C4190 (Other numerical methods) Thesaurus: Circuit analysis computing; Convergence of numerical methods; Eigenvalues and eigenfunctions; Optimisation; Packaging Free Terms: Signal propagation parameters; Electronic packages; Electromagnetic codes optimisation; Propagation characteristics; Package structures; Numerical convergence; 3D problems; Run time Item Availability: CD-ROM. INSPEC 4823407 B9412-0170J-058 Doc Type: Conference Paper Title: The correlation of shear stress and metal shift: a modeling approach (packaging) Authors: Kelly, G.; Lyden, C.; O'Mathuna, C.; Slattery, O.; Hayes, T.; Exposito, J. Affiliation: Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 264-9 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0264$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Theoretical/Mathematical Abstract: This paper uses three dimensional finite element methods to determine the thermo-mechanically induced encapsulation stress in a 160 lead plastic quad flat pack. Comparisons are made between the effects of different leadframe materials on die stress. The degree of discretisation of the leadframe necessary to accurately model its effect on die stress is determined. A strong correlation between metal shift and out of plane shear stress is proposed following comparisons of FE package modeling and experimentally measured metal shift patterns on specially developed test die. (8 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis) Thesaurus: Deformation; Encapsulation; Finite element analysis; Modelling; Simulation; Stress effects; Surface mount technology; Thermal stresses Free Terms: Shear stress; Metal shift; 3D finite element methods; Thermo-mechanically induced encapsulation stress; 3D FEM; Leadframe materials; Die stress; Out of plane shear stress; FE package modeling; Shift patterns Item Availability: CD-ROM. INSPEC 4823405 B9412-0170J-056 C9412-7430-005 Doc Type: Conference Paper Title: Application of a CFD tool for system level thermal simulation Authors: Lee, T.; Mahalingam, M. Affiliation: Adv. Packaging Dev. Center, Motorola Inc., Phoenix, AZ, USA Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 249-55 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0249$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Theoretical/Mathematical Abstract: A Computational Fluid Dynamics (CFD) tool is used to evaluate the velocity and the temperature fields of air flow in a computer system enclosure. Simulations focused on the six printed circuit board regions where approximately 37 W of power was generated on the component side of the board. Three-dimensional, steady-state, turbulent air flow is assumed. Solutions include pressure, velocities, and temperature. Both straight and swirl flow cases at fans were considered. The actual air flow rate at fans was determined by matching the predicted pressure rise across the fan to the given fan characteristics. Experiments were performed under real life conditions. The actual computer chassis was tested inside a temperature-controlled chamber. Air temperatures between two printed circuit boards were measured in various positions and compared with the simulations. Results demonstrate a reasonable agreement between the temperatures obtained by simulations and measurements. In all comparisons, average errors were less than 10%. The introduction of swirl at fans made no significant effect on temperatures. A hot spot appeared in the inner side of the air passage between boards; this hot spot was created due to the recirculation of low velocity air. Some recommendations on improvements of the simulation are also presented. (3 Refs.) Classification: B0170J (Product packaging); C7430 (Computer engineering); C5490 (Other aspects of analogue and digital computers); C6185 (Simulation techniques) Thesaurus: Computers; Digital simulation; Fluid dynamics; Packaging; Simulation; Temperature distribution; Thermal analysis; Turbulence Free Terms: CFD tool; System level thermal simulation; Computational fluid dynamics; Air flow velocity; Temperature fields; Computer system enclosure; Printed circuit board regions; 3D steady-state turbulent air flow; Swirl flow; Fans; Hot spot Item Availability: CD-ROM. INSPEC 4823394 B9412-0170J-050 Doc Type: Conference Paper Title: On-chip piezoresistive stress measurement and 3D finite element simulations of plastic DIL 40 packages using different materials Authors: van Gestel, H.C.J.M.; van Gemert, L.; Bagerman, E. Affiliation: Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 124-33 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0124$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Theoretical/Mathematical; Experimental Abstract: A full matrix of 8 different configurations of a plastic DIL 40 package has been measured. The materials used in the package consisted of a copper or an alloy 42 lead frame, a standard conductive die-attach adhesive or a special low stress type of die-attach adhesive and a standard moulding compound or a low stress compound. The stress measurements were performed with a test chip based on the piezoresistive effect. The numerical simulations ham been carried out to verify the results and to gain more insight in the deformations inside the package. Though the results are achieved for an dual in line package some results will also be valid for other types of plastic packages. (5 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis); B7320G (Mechanical variables measurement); B2860 (Piezoelectric and ferroelectric devices); B7230 (Sensing devices and transducers) Thesaurus: Deformation; Finite element analysis; Integrated circuit technology; Integrated circuit testing; Modelling; Packaging; Piezoelectric transducers; Simulation; Strain gauges; Stress analysis; Stress measurement Free Terms: Onchip piezoresistive stress measurement; 3D finite element simulations; Plastic DIL 40 packages; Cu lead frame; Alloy 42 lead frame; Conductive die-attach adhesive; Standard moulding compound; Low stress compound; Piezoresistive effect; Numerical simulation; Deformations; Dual inline package; Cu; Ni-Fe Chemical Index: Cu/el; NiFe/bin Fe/bin Ni/bin Item Availability: CD-ROM. INSPEC 4823387 B9412-0170J-049 Doc Type: Conference Paper Title: Reliability and thermal characterization of a 3-dimensional multichip module Authors: Lin, A.W.; Lyons, A.M.; Simpkins, P.G. Affiliation: AT&T Bell Labs., Murray Hill, NJ, USA Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 71-9 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0071$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Experimental Abstract: Three dimensional packaging extends the high interconnection density which has been achieved using multichip modules to a new dimension. In this paper, we describe the fabrication of an unique 3-dimensional multichip module (3-D MCM) based on AT&Ts Si-on-Si Micro Interconnect technology. Four multichip tiles are interconnected on a multilayer metal-core printing wiring board. Eight such boards are then stacked vertically to form a 3-D module. Compliant anisotropically conductive elastomers are the key element in this design providing electrical interconnection between the stacked boards. The heat generated by the multichip tiles is conducted to the metal-core board and removed by air forced through holes on the perimeter of the boards. This paper describes results of a reliability evaluation of the vertical interconnect scheme. In addition a thermal characterization of the 3-D module is presented. (5 Refs.) Classification: B0170J (Product packaging); B0170N (Reliability); B0170E (Production facilities and engineering); B2210 (Printed circuits) Thesaurus: Circuit reliability; Cooling; Elastomers; Multichip modules; Printed circuit testing; Thermal analysis Free Terms: Reliability evaluation; Thermal characterization; 3-Dimensional MCM; 3D multichip module; Three dimensional packaging; High interconnection density; Fabrication; Si-on-Si Micro Interconnect technology; Multilayer metal-core PWB; Printing wiring board; Vertically stacked boards; Anisotropically conductive elastomers; Electrical interconnection; Forced air cooling Item Availability: CD-ROM. INSPEC 4823380 B9412-1265D-072 C9412-5320G-037 Doc Type: Conference Paper Title: Evaluation of a 3D memory cube system Authors: Bertin, C.L.; Perlman, D.J.; Shanken, S.N. Affiliation: IBM Corp., Essex Junction, VT, USA Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 12-15 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0012$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Practical; Experimental Abstract: Silicon 'cubes' consisting of 18-20 1 Mbit DRAM chips have been fabricated jointly by IBM and Irvine Sensors Corporation. In the stack process, the chips are joined by adhesive to form the cube, interconnected by chip metalization processes, packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1 Mbit DRAM memory modules that normally form the card array. Memory cube operation is verified by testing both original and cube memory card on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines and PGA substrate was performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines. (0 Refs.) Classification: B1265D (Memory circuits); B0170J (Product packaging); C5320G (Semiconductor storage) Thesaurus: Add-on boards; DRAM chips; Integrated circuit testing; Packaging; Redundancy; Semiconductor storage Free Terms: 3D memory cube system; DRAM chips; IBM; Irvine Sensors Corporation; Stack process; Adhesive; Chip metalization processes; Ceramic pin grid array; PGA substrate; Memory card; Testing; Electrical modeling; Simulation; Cube interconnect circuitry; Interchip bus lines; Interconnect redundancy; Wiring redundancy; 1 Mbit; 18 To 20 Mbit Numerical Index: Storage capacity 1.0E+06 bit; Storage capacity 1.9E+07 to 2.1E+07 bit Item Availability: CD-ROM. INSPEC 4805942 B9412-6320E-014 C9412-7440-025 Doc Type: Conference Paper Title: Effect of cable and towbody parameters on tension and cable length when towing at 200 m depths and 10 knots Authors: Latchman, S. Affiliation: Defence Res. Establ. Pacific, FMO Victoria, BC, Canada Conf. Title: OCEANS '93. Engineering in Harmony with Ocean Proceedings (Cat. No.93CH3341-5) p. III491-6 vol.3 Publisher: IEEE New York, NY, USA Date: 1993 3 vol. (xxiii+491+509+502 pp.) Country of Publication: USA ISBN: 0 7803 1385 2 CCC: 0 7803 1385 2/93/$3.00 Language: English Conf. Date: 18-21 Oct. 1993 Conf. Loc: Victoria, BC, Canada Conf. Sponsor: Oceanic Eng. Soc. IEEE and its Victoria Chapter; B.C. Trade Dev. Corp Treatment: Application; Practical Abstract: This paper presents the results of a simulation study on steady state towing of a towbody at a depth of 200 meters and a speed of 10 knots. BCABLE, a three-dimensional dynamic cable simulation program was used to study the effect on tension and cable length of the cable parameters of specific gravity, diameter, and drag coefficients (Including cable fairings), and towbody parameters such as weight, lift and drag. This study is applicable to route survey operations for mine countermeasures (MCM) and other side scan sonar search and survey operations using the new multi-beam side scan sonars. (9 Refs.) Classification: B6320E (Sonar and acoustic radar); B7710D (Oceanographic and hydrological techniques and equipment); B0590 (Materials testing); C7440 (Civil and mechanical engineering computing); C6185 (Simulation techniques) Thesaurus: Cable testing; Digital simulation; Mechanical engineering; Mechanical engineering computing; Mechanical testing; Sonar Free Terms: Towbody parameters; Cable parameters; Tension; Cable length; Depths; Knots; Simulation study; Steady state towing; BCABLE; 3D dynamic cable simulation program; Specific gravity; Diameter; Drag coefficients; Cable fairings; Weight; Lift; Drag; Route survey operations; Mine countermeasures; Multibeam side scan sonars; 200 M Numerical Index: Depth 2.0E+02 m Item Availability: CD-ROM. INSPEC 4805038 B9412-1130B-069 C9412-7410D-099 Doc Type: Conference Paper Title: A general purpose 3D electromagnetic simulation and optimization package-IE3D Authors: Jian-Xiong Zheng Affiliation: Zeland Software Inc., San Francisco, CA, USA Conf. Title: 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4) p. 373-6 vol.1 Editors: Kuno, H.J.; Wen, C.P. Publisher: IEEE New York, NY, USA Date: 1994 3 vol. (xxxiii+xlvii+1788+xxviii+xviii+xli pp.) Country of Publication: USA ISBN: 0 7803 1778 5 CCC: CH3389-4/94/0000-0373$01.00 Language: English Conf. Date: 23-27 May 1994 Conf. Loc: San Diego, CA, USA Treatment: Application; Practical Abstract: A general purpose electromagnetic simulation and optimization package IE3D has been developed for the analysis and design of planar and 3D structures encountered in microwave and millimeter-wave integrated circuits (MMIC), high temperature superconductor (HTS) circuits, microstrip antennas, RF printed circuit boards (PCB) and high speed digital circuit packaging. Based upon an integral equation, method of moment algorithm, the simulator can accurately and efficiently simulate arbitrarily shaped and oriented 3D metallic structures in multi-layer dielectric substrates. The simulator is interfaced with standard MS-Windows based layout editor, schematic editor and post processor. The IE3D simulation results compared with measured results are presented in this paper. (7 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B1350H (Microwave integrated circuits); B3240C (Superconducting junction devices); B1320 (Waveguide components); B0170J (Product packaging); B0290R (Integral equations); B2210B (Printed circuit layout and design); C7410D (Electronic engineering computing); C4180 (Integral equations) Thesaurus: Circuit layout CAD; Digital simulation; High-temperature superconductors; Integral equations; Microstrip antennas; Microwave integrated circuits; Numerical analysis; Packaging; Printed circuits; Software packages; Superconducting integrated circuits; Superconducting microwave devices Free Terms: 3D electromagnetic simulation; IE3D; Electromagnetic package; Planar structures; 3D structures; Microwave integrated circuits; Millimeter-wave integrated circuits; High temperature superconductor circuits; Microstrip antennas; RF printed circuit boards; High speed digital circuit packaging; Integral equation; Method of moment algorithm; Metallic structures; Multi-layer dielectric substrates; MS-Windows based layout editor; Schematic editor Item Availability: CD-ROM. INSPEC 4795702 B9411-1350H-145 Doc Type: Conference Paper Title: Via hole, bond wire and shorting pin modeling for multi-layered circuits Authors: Ming-Ju Tsai; Tzyy-Sheng Horng; Alexopoulos, N.G. Affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA Conf. Title: 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4) p. 1777-80 vol.3 Editors: Kuno, H.J.; Wen, C.P. Publisher: IEEE New York, NY, USA Date: 1994 3 vol. (xxxiii+xlvii+1788+xxviii+xviii+xli pp.) Country of Publication: USA ISBN: 0 7803 1778 5 CCC: CH3389-4/94/0000-1777$01.00 Language: English Conf. Date: 23-27 May 1994 Conf. Loc: San Diego, CA, USA Treatment: Theoretical/Mathematical Abstract: This paper presents a full-wave spectral-domain analysis to model generalized three-dimensional circuits for multilayered structures. To describe properly the current along the vertical post, such as via holes, bond wires and shorting pins, etc., the simple pulse function is used in the procedure of the moment method. Several numerical techniques are applied to improve the evaluation of matrix elements. Comparison of numerical results with experimental and available analytical data shows good agreement. (10 Refs.) Classification: B1350H (Microwave integrated circuits); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits); B0290Z (Other numerical methods) Thesaurus: Microstrip components; Microwave integrated circuits; MMIC; Modelling; Numerical analysis; Packaging; Spectral-domain analysis Free Terms: Via hole modelling; Bond wire modelling; Shorting pin modeling; Multilayered circuits; Full-wave spectral-domain analysis; Three-dimensional circuits; Multilayered structures; Pulse function; Moment method; Numerical techniques; Matrix elements; 3D microstrip circuits Item Availability: CD-ROM. INSPEC 4795690 B9411-0170J-123 Doc Type: Conference Paper Title: 3D FDTD analysis applied to the investigation of the resonant behavior of ceramic feedthrus Authors: Rittweger, M.; Werthen, M.; Wolff, I. Affiliation: Inst. fur Mobil- und Satellitenfunktechnik, Kamp-Lintfort, Germany Conf. Title: 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4) p. 1719-22 vol.3 Editors: Kuno, H.J.; Wen, C.P. Publisher: IEEE New York, NY, USA Date: 1994 3 vol. (xxxiii+xlvii+1788+xxviii+xviii+xli pp.) Country of Publication: USA ISBN: 0 7803 1778 5 CCC: CH3389-4/94/0000-1719$01.00 Language: English Conf. Date: 23-27 May 1994 Conf. Loc: San Diego, CA, USA Treatment: Theoretical/Mathematical Abstract: Ceramic feedthrus provide hermetically sealed interconnections for many different package types. Just as with the package itself the transfer function of the feedthru is affected by resonances. The application of the three-dimensional finite difference time-domain method is a straight forward technique to simulate such effects. Special consideration is given to the basic resonance mechanisms by building up the feedthru step by step. The simulated results from these structures are examined and for specific examples comparison with measured results is shown. (3 Refs.) Classification: B0170J (Product packaging); B0290Z (Other numerical methods) Thesaurus: Ceramics; Finite difference time-domain analysis; Packaging; Transfer functions Free Terms: 3D FDTD analysis; Ceramic feedthrus; Hermetically sealed interconnections; Packages; Transfer function; Resonances; Three-dimensional finite difference time-domain method; Simulation Item Availability: CD-ROM. INSPEC 4795688 B9411-1350H-136 Doc Type: Conference Paper Title: Rigorous field theory analysis of flip-chip interconnections in MMICs using the FDTLM method Authors: Jin, H.; Vahldieck, R.; Minkus, H.; Huang, J. Affiliation: Lab. for Lightwave Electron., Microwaves & Commun., Victoria Univ., BC, Canada Conf. Title: 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4) p. 1711-14 vol.3 Editors: Kuno, H.J.; Wen, C.P. Publisher: IEEE New York, NY, USA Date: 1994 3 vol. (xxxiii+xlvii+1788+xxviii+xviii+xli pp.) Country of Publication: USA ISBN: 0 7803 1778 5 CCC: CH3389-4/94/0000-1711$01.00 Language: English Conf. Date: 23-27 May 1994 Conf. Loc: San Diego, CA, USA Treatment: Theoretical/Mathematical Abstract: This paper presents a rigorous 3-D field theory analysis of the flip-chip assembly by using the frequency-domain TLM method. The scattering parameters of the bump discontinuities are calculated in the cases of CPW and microstrip. Simulation results show that the flip-chip packaging using solder bump connecting the mother board and the chip provides better electrical performance in comparison with the conventional wire bonding approach. With the dimensions used in this paper, the reflections at the bump discontinuities are found to be better than -40 dB and -20 dB, respectively, for CPW and microstrip over the frequency spectrum from 1 GHz to 40 GHz. (4 Refs.) Classification: B1350H (Microwave integrated circuits); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B2240 (Microassembly techniques) Thesaurus: Flip-chip devices; Frequency-domain analysis; Integrated circuit technology; MMIC; Transmission line theory Free Terms: Reflections; Flip-chip interconnections; MMICs; 3-D field theory analysis; Assembly; Frequency-domain TLM method; Scattering parameters; Bump discontinuities; CPW; Microstrip; Simulation; Packaging; Solder bump; Electrical performance; 1 To 40 GHz Numerical Index: Frequency 1.0E+09 to 4.0E+10 Hz Item Availability: CD-ROM. INSPEC 4780863 B9411-1350H-018 Doc Type: Journal Paper Title: Analysis of microwave capacitors and IC packages Authors: Beker, B.; Cokkinides, G.; Templeton, A. Affiliation: Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA Journal: IEEE Transactions on Microwave Theory and Techniques Vol: 42 Iss: 9, pt.2 p. 1759-64 Date: Sept. 1994 Country of Publication: USA ISSN: 0018-9480 CODEN: IETMAB CCC: 0018-9480/94/$04.00 Language: English Treatment: Practical; Theoretical/Mathematical Abstract: This paper presents quasi-static electromagnetic (EM) models for analysis and design of microwave capacitors and integrated circuit (IC) packages. The theoretical background for modeling of open 3-D boundaries with finite difference method (FDM) is reviewed and the use of current simulation method (CSM) for inductance computation is proposed. Computed data for the capacitance and inductance of capacitors with complex three-dimensional geometries are verified both numerically and experimentally, validating the proposed quasi-static models. Numerical results for practical devices and IC packages are also given. (17 Refs.) Classification: B1350H (Microwave integrated circuits); B2130 (Capacitors); B0170J (Product packaging); B0290P (Differential equations) Thesaurus: Capacitance; Capacitors; Finite difference methods; Inductance; Microwave integrated circuits; Packaging Free Terms: Microwave capacitors; Microwave IC packages; Quasi-static electromagnetic models; Open 3D boundaries; Finite difference method; Current simulation method; Inductance computation; Three-dimensional geometries Item Availability: CD-ROM. INSPEC 4780862 B9411-0170J-035 C9411-7410D-098 Doc Type: Journal Paper Title: FASTHENRY: a multipole-accelerated 3-D inductance extraction program Authors: Kamon, M.; Ttsuk, M.J.; White, J.K. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Journal: IEEE Transactions on Microwave Theory and Techniques Vol: 42 Iss: 9, pt.2 p. 1750-8 Date: Sept. 1994 Country of Publication: USA ISSN: 0018-9480 CODEN: IETMAB CCC: 0018-9480/94/$04.00 Language: English Treatment: Application; Practical; Theoretical/Mathematical Abstract: A mesh analysis equation formulation technique combined with a multipole-accelerated Generalized Minimal Residual (GMRES) matrix solution algorithm is used to compute the 3-D frequency dependent inductances and resistances in nearly order n time and memory where n is the number of volume-filaments. The mathematical formulation and numerical solution are discussed, including two types of preconditioners for the GMRES algorithm. Results from examples are given to demonstrate that the multipole acceleration can reduce required computation time and memory by more than an order of magnitude for realistic integrated circuit packaging problems. (14 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing); C4185 (Finite element analysis) Thesaurus: Circuit analysis computing; Inductance; Mesh generation; Packaging Free Terms: FASTHENRY; Multipole-accelerated 3D inductance extraction program; Mesh analysis equation formulation technique; Generalized minimal residual matrix; Preconditioners; Computation time; Integrated circuit packaging problems Item Availability: CD-ROM. INSPEC 4774694 B9411-8320-006 Doc Type: Conference Paper in Journal Title: Magnetic field analysis and optimal design of DC permanent magnet coreless disc machine Authors: Gu, C.L.; Wu, W.; Shao, K.R. Affiliation: Dept. of Electr. Eng., Huazhong Univ. of Sci. & Technol., Hubei, China Journal: IEEE Transactions on Magnetics Vol: 30 Iss: 5, pt.2 p. 3668-71 Date: Sept. 1994 Country of Publication: USA ISSN: 0018-9464 CODEN: IEMGAQ CCC: 0018-9464/94/$4.00 Language: English Conf. Title: 9th Conference on the Computation of Electromagnetic Fields (COMPUMAG '93) Conf. Date: 31 Oct.-4 Nov. 1993 Conf. Loc: Miami, FL, USA Conf. Sponsor: IEEE Miami Sect.; IEEE Florida Council; IEEE Region 3, USA; IEE Japan; IEE UK; Magnetic Soc.; Applied Computational Electromagn. Soc.; Florida Int. Univ.; Digital Equipment; Vector Fields; Infolytica; GE Transport. Syst.; IBM; Alps Electric; Ansoft; Appl. Electromagn. Center; DAEWOO Electron.; Hyosung Ind.; Integrated Eng. Software; Matsushita Electr. Ind.; Samsung Electro-Mech.; Swansen Analysis Syst.; Florida Int. Univ Treatment: Theoretical/Mathematical Abstract: The magnetic field in a DC permanent magnet coreless disc machine is studied in depth by using different methods, such as three dimensional finite element method (3DFEM), two dimensional finite element method (2DFEM) and magnetic circuit method (MCM) based on an analytical solution. For optimization, the cases for different magnet dimensions, airgap lengths and configurations are investigated in detail. Numerical results show that if the field is provided by the ferrite magnets, the ratio of magnet thickness to airgap length should be greater than 3 and the distance from magnet to stator wall or the width of the magnetism-free channels between two adjacent poles should be greater than 6 mm. Moreover, both 2DFEM and MCM are feasible for general optimal design purpose focusing on practicality and time saving. (7 Refs.) Classification: B8320 (d.c. machines); B5120 (Magnetostatics); B0290T (Finite element analysis) Thesaurus: DC machines; Finite element analysis; Machine theory; Magnetic circuits; Magnetic fields; Optimisation; Permanent magnet machines Free Terms: Magnetic field analysis; Optimal design; DC permanent magnet machine; Coreless disc machine; Three dimensional FEM; Finite element method; 3D FEM; Two dimensional FEM; 2D FEM; Magnetic circuit method; Analytical solution; Optimization; Magnet dimensions; Airgap lengths; Ferrite magnets Item Availability: CD-ROM. INSPEC 4774515 B9411-8350-009 Doc Type: Journal Paper Title: Three-dimensional flux distributions in transformer cores as a function of package design Authors: Pfutzner, H.; Bengtsson, C.; Booth, T.; Loffler, F.; Gramm, K. Affiliation: Univ. of Technol., Vienna, Austria Journal: IEEE Transactions on Magnetics Vol: 30 Iss: 5, pt.1 p. 2713-27 Date: Sept. 1994 Country of Publication: USA ISSN: 0018-9464 CODEN: IEMGAQ CCC: 0018-9464/94/$04.00 Language: English Treatment: Experimental Abstract: In spite of extensive optimizations of transformer core designs, investigations of full sized cores showed distinct inhomogeneities of flux density B. Limbs showed discontinuous variations of B in peripheral packages and minima of B in thick central ones. The latter are not caused by global eddy currents but rather by localized flux components Phi /sub z/ normal to the sheet plane. Attempts to determine the respective effective ac-permeability mu /sub z/ yielded values below 100, i.e., almost three orders below mu /sub x/ of the rolling direction. For given B, (planar) eddy current losses P/sub z/ proved to exceed the respective values P/sub x/ by two orders, a ratio which increases with increasing length L of the magnetized sheet region. The low ratio mu /sub z// mu /sub x/ yields a tendency of constant package flux throughout the whole core. A key criterium for Phi /sub z/-components between packages proved to be the overlap regions which were studied in a comparative way for several step-lap configurations. Distinct differences of respective values of lap-region excitation V/sub L/ were observed as a function of air gap lengths and the step number N, respectively. Variations of V/sub l/-and especially overlaps of high V/sub L/ in connection with shifted overlap regions-proved to yield Phi /sub z/-components including flux transfer between packages. In a complex way, shifts yielded decreasing excitation power, but increased core losses due to planar eddy currents. In addition, package shifts cause both the discontinuities of B of thin peripheral packages and the minima of local B in thick central ones. With respect to core design, it can be assumed that small shifts favor take over of flux without causing significant planar eddy current losses (due to small L), while large shifts increase total losses in a disadvantageous way. With increasing N, these effects become less significant. (18 Refs.) Classification: B8350 (Transformers and reactors); B3120D (Magnetic cores); B0170J (Product packaging) Thesaurus: Eddy current losses; Magnetic cores; Magnetic flux; Magnetic permeability; Packaging; Power transformers; Transformer cores Free Terms: Three-dimensional flux distributions; Transformer cores; Package design; Effective AC-permeability; Planar eddy current losses; Magnetized sheet; Step-lap configurations; Air gap; Core losses; Excitation power; Overlaps Item Availability: CD-ROM. INSPEC 4765712 B9411-1265F-003 C9411-5135-002 Doc Type: Journal Paper Title: 3D-WASP devices for on-line signal and data processing Authors: Hedge, S.J.; Habiger, C.M.; Lea, R.M. Affiliation: Aspex Microsystems Ltd., Brunel Univ., Uxbridge, UK Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 17 Iss: 3 p. 324-33 Date: Aug. 1994 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/94/$04.00 Language: English Treatment: Practical Abstract: While hybrid and monolithic Wafer-Scale Integration (WSI) technologies have brought about dramatic improvements in the density of integration of embedded massively parallel computers (MPCs), systems and applications engineers continue to demand ever more processing power in less space. The emerging technology of 3D-WSI offers a way of meeting this challenge, giving the potential for step-function increases in parallelism using existing WSI package options. It also permits independent scaling of I/O, parallel processing power and control, leading to a degree of cost-effectiveness that conventional 2D-WSI cannot match. The paper explores the potential of 3D-WASP (WSI Associative String Processor) and reports the results of a study into the engineering feasibility of such a device. This study suggests that a single 3D-WASP device, packages in a standard 2.5'*2.5'*0.25' can could deliver 100 Giga-OPS performance form 65536 processing elements, provide up to 64 input-output data channels of 16 bits each and dissipate only 25 W. (3 Refs.) Classification: B1265F (Microprocessors and microcomputers); C5135 (Digital signal processing chips); B2570 (Semiconductor integrated circuits); B6140 (Signal processing and detection); C5220P (Parallel architecture); C5260 (Digital signal processing); B0170J (Product packaging) Thesaurus: Digital signal processing chips; Packaging; Parallel architectures; VLSI Free Terms: 3D-WASP devices on-line signal processing on-line data processing massively parallel computers Wafer-Scale Integration 3D-WSI package WSI Associative String Processor 100 Giga-OPS input-output data channels; 16 Bit; 25 W; 2.5 In; 0.25 In Numerical Index: Word length 1.6E+01 bit; Power 2.5E+01 W; Size 6.4E-02 m; Size 6.3E-03 m Item Availability: CD-ROM. INSPEC 4710818 B9408-1210-039 Doc Type: Conference Paper Title: Thermal design principles and characterization of miniaturized surface-mount packages for power electronics Authors: Kasem, Y.M.; Williams, R.K. Affiliation: Siliconix Inc., Santa Clara, CA, USA Conf. Title: Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs ISPSD '93 (Cat. No.93CH3314-2) p. 316-21 Editors: Williams, R.K.; Baliga, B.J. Publisher: IEEE New York, NY, USA Date: 1993 xviii+324 pp. Country of Publication: USA ISBN: 0 7803 1313 5 CCC: 0 7803 1313 5/93/$3.00 Language: English Conf. Date: 18-20 May 1993 Conf. Loc: Monterey, CA, USA Conf. Sponsor: IEEE; Inst. Electr. Eng. Japan Treatment: Practical; Theoretical/Mathematical Abstract: The major factors affecting the power dissipation capabilities of SOIC packages, including lead-frame design, airflow, and board and ambient temperatures, are presented. Results show that modifying an eight-lead SOIC package with a four-lead power tab increases the package's power dissipating capabilities to beyond 2 W for natural convection cooling, more than double that of a standard SO-8 package. Extensive 3D finite element thermal studies reveal that, while the modified package exhibits a thermal resistance of 28 degrees C/W, the PC (printed circuit) board typically contributes an additional 34 degrees C/W. It is demonstrated that the finite element method significantly contributes to the ability of a system designer to optimally utilize space-efficient SOIC packages from a series of parametric choices and tradeoffs. The effect of package and circuit board on the maximum power dissipation and junction temperature of surface-mounted power MOSFETs is thus clarified. (5 Refs.) Classification: B1210 (Power electronics, supply and supervisory circuits); B0170J (Product packaging); B2210B (Printed circuit layout and design); B0290T (Finite element analysis) Thesaurus: Cooling; Finite element analysis; Packaging; Power electronics; Printed circuit design; Surface mount technology Free Terms: Board temperatures; Thermal design; Miniaturized surface-mount packages; Power electronics; Power dissipation capabilities; Lead-frame design; Airflow; Ambient temperatures; Eight-lead SOIC package; Four-lead power tab; Power dissipating capabilities; Natural convection cooling; 3D finite element thermal studies; Thermal resistance; Junction temperature Item Availability: CD-ROM. INSPEC 4705988 B9408-1130B-018 C9408-7410D-078 Doc Type: Conference Paper Title: A fast four-via multilayer MCM router Authors: Khoo, K.-Y.; Cong, J. Affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA Conf. Title: Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93 (Cat. No.93CH3224-3) p. 179-84 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1993 xi+203 pp. Country of Publication: USA ISBN: 0 8186 3540 1 CCC: 0 8186 3540 1/93/$3.00 Language: English Conf. Date: 15-18 March 1993 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: An efficient multilayer general area router, named V4, for MCM and dense PCB designs is presented. The unique feature of the V4 router is that it uses no more than four vias to route every net and yet produces high quality routing solutions. A number of combinatorial optimization techniques are used in the router to produce high quality routing solutions in polynomial time. As a result, it is independent of net ordering, runs much faster, and has far less memory requirement compared to other multilayer general area routers. The router was tested on several examples, including two industrial MCM designs. Compared with the 3-D maze router, on average the V4 router uses 2% less wire length, 31% fewer vias, and runs 26 times faster. Compared with the SLICE router, on average the V4 router uses 4% less wire length and runs 4.6 times faster. (17 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B0170J (Product packaging); B2210B (Printed circuit layout and design); C7410D (Electronic engineering computing) Thesaurus: Circuit layout CAD; Multichip modules; Network routing; Printed circuit design Free Terms: 3D maze router; Four-via multilayer MCM router; General area router; Dense PCB designs; V4 router; Combinatorial optimization techniques; Polynomial time; Net ordering; Industrial MCM designs; Wire length; SLICE router Item Availability: CD-ROM. INSPEC 4705972 B9408-0170J-030 Doc Type: Conference Paper Title: A quasi-static analysis of fuzz button interconnects Authors: Pan, G.; Zhu, X.; Gilbert, B. Affiliation: Dept. of Electr. Eng. & Comput. Sci., Wisconsin Univ., Milwaukee, WI, USA Conf. Title: Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93 (Cat. No.93CH3224-3) p. 85-91 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1993 xi+203 pp. Country of Publication: USA ISBN: 0 8186 3540 1 CCC: 0 8186 3540 1/93/$3.00 Language: English Conf. Date: 15-18 March 1993 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: Theoretical/Mathematical Abstract: In the analysis, by using the equivalence principle, a set of integral equations is established and solved by a combined point-matching and Galerkin's method. An iterative algorithm is proposed to solve the matrix equations. The inductance is found by the power-current definition. An equivalent nonuniform transmission line is established and waveform simulation is conducted. The results are compared with FDTD results and good agreement is observed. (5 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B0220 (Mathematical analysis); B0290F (Interpolation and function approximation); B0290R (Integral equations) Thesaurus: Finite difference time-domain analysis; Integral equations; Iterative methods; Multichip modules Free Terms: Point matching method; Numerical method; Finite difference time domain algorithm; 3D diamond substrate MCM; Magnetostatic analysis; Electrostatic analysis; Quasi-static analysis; Fuzz button interconnects; Equivalence principle; Integral equations; Galerkin's method; Iterative algorithm; Inductance; Power-current definition; Equivalent nonuniform transmission line; Waveform simulation; FDTD Item Availability: CD-ROM. INSPEC 4695427 B9408-0170J-008 Doc Type: Conference Paper Title: Reliability technology to achieve insertion of advanced packaging (RELTECH) program Authors: Fayette, D.F.; Speicher, P.; Stoklosa, M.; Evans, J.; Evans, J.; Gentile, M.; Hakim, E. Affiliation: Rome Lab., Griffiss AFB, NY, USA Conf. Title: Proceedings of the IEEE 1993 National Aerospace and Electronics Conference. NAECON 1993 (Cat. No.93CH3306-8) p. 223-9 vol.1 Publisher: IEEE New York, NY, USA Date: 1993 2 vol. xvii+1171 pp. Country of Publication: USA ISBN: 0 7803 1295 3 CCC: CH3306-8/93/0000-0223$1.00 Language: English Conf. Date: 24-28 May 1993 Conf. Loc: Dayton, OH, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: This paper describes a joint military/commercial effort to evaluate MCM structures and represents a model for future reliability studies for other technologies. The first MCM technology evaluated is General Electric's High Density Interconnect (HDI) structure, followed by nChips nC1000 process, IBM VCOS technology, Motorola's C5 process on laminate, Martin Marietta chip-on-board (COB) technology and 3D stacks. The RELTECH program and the military specification activity is expected to result in a risk free transition of MCMs into DOD and commercial systems. (0 Refs.) Classification: B0170J (Product packaging); B0170N (Reliability); B7630 (Avionic systems and aerospace instrumentation); B7910 (Military circuits, components, and equipment); B0170E (Production facilities and engineering) Thesaurus: Aerospace instrumentation; Electronic equipment testing; Environmental testing; Life testing; Military equipment; Multichip modules; Reliability Free Terms: Joint military/commercial effort; Packaging; RELTECH; MCM structures; Reliability; General Electric; High Density Interconnect; NChips nC1000 process; IBM VCOS technology; Motorola; C5 process on laminate; Martin Marietta; Chip-on-board technology; 3D stacks; COB; DoD; NASA; FEA; Accelerated testing; Environmental testing Item Availability: CD-ROM. INSPEC 4684229 B9407-1350H-017 Doc Type: Journal Paper Title: Finite element analysis of MMIC structures and electronic packages using absorbing boundary conditions Authors: Wang, J.-S.; Mittra, R. Affiliation: Swanson Anal. Syst. Inc., Houston, PA, USA Journal: IEEE Transactions on Microwave Theory and Techniques Vol: 42 Iss: 3 p. 441-9 Date: March 1994 Country of Publication: USA ISSN: 0018-9480 CODEN: IETMAB CCC: 0018-9480/94/$04.00 Language: English Treatment: Theoretical/Mathematical Abstract: In this paper, a three-dimensional finite element method (FEM) is employed in conjunction with first and second-order absorbing boundary conditions (ABC's) to analyze waveguide discontinuities and to derive their scattering parameters. While the application of FEM for the analysis of MMIC structures is not new, to the best of the knowledge of the authors the technique for mesh truncation for microstrip lines using the first and higher-order ABC's, described in this paper, has not been reported elsewhere. The scattering parameters of a microstrip discontinuity are computed in two steps. As a first step, the field distribution of the fundamental mode in a uniform microstrip is obtained by exciting the uniform line with the quasi-static transverse electric field, letting it propagate, and then extracting the dominant mode pattern after the higher order modes have decayed. In step two, the discontinuity problem is solved by exciting the structure by using the fundamental mode obtained in step one. The scattering parameters based on the voltage definition are calculated by using the line integral of electric fields underneath the strip. Numerical solutions for several waveguide discontinuities and electronic packages are obtained and compared with the published data. (12 Refs.) Classification: B1350H (Microwave integrated circuits); B0170J (Product packaging); B0290T (Finite element analysis); B0290R (Integral equations); B5240D (Waveguide and cavity theory) Thesaurus: Boundary-elements methods; Boundary-value problems; Finite element analysis; Integral equations; Microstrip lines; MMIC; Packaging; S-parameters; Waveguide theory Free Terms: Three-dimensional FEM; Finite element method; MMIC structures; Electronic packages; Absorbing boundary conditions; 3D FEM; Waveguide discontinuities; Scattering parameters; Mesh truncation; Microstrip lines; Microstrip discontinuity; Field distribution; Fundamental mode; Quasi-static transverse electric field; Dominant mode pattern; Voltage definition; Line integral Item Availability: CD-ROM. INSPEC 4677989 B9407-4180-014 C9407-5270-008 Doc Type: Conference Paper Title: Optical interconnects based on two-dimensional VCSEL arrays Authors: Neff, J.A. Affiliation: Optoelectron. Comput. Syst. Center, Colorado Univ., Boulder, CO, USA Conf. Title: Proceedings of the First International Workshop on Massively Parallel Processing Using Optical Interconnections p. 202-12 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 x+332 pp. Country of Publication: USA ISBN: 0 8186 5832 0 CCC: 0 8186 5832 0/94/$3.00 Language: English Conf. Date: 26-27 April 1994 Conf. Loc: Cancun, Mexico Conf. Sponsor: IEEE; ACM; AFOSR Treatment: Practical Abstract: Free space optical interconnects offer an exciting alternative to conventional packaging for electronic systems which uses planar board and backplane structures. The alternative, which shall be called 3D packaging, involves using the space perpendicular to the processing planes for free-space optical beams that transport the data between the planes. 3D packaging is very appealing for tightly-coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes an effort to develop the enabling technologies for these 3D systems, and to demonstrate a functional computer based on this technology. The approach is to realize the optical interconnections through the use of two-dimensional optoelectronic (smart pixel) arrays based on vertical-cavity surface-emitting laser arrays. (7 Refs.) Classification: B4180 (Optical logic devices and optical computing techniques); B4270 (Integrated optoelectronics); C5270 (Optical computing techniques); C5220P (Parallel architecture) Thesaurus: Optical information processing; Optical interconnections; Packaging; Parallel architectures Free Terms: Free space optical interconnects; Backplane structure; Planar board; 2D VCSEL arrays; Free-space optical beams; 3D packaging; Tightly-coupled fine-grained parallel computing; Optoelectronic arrays; Smart pixel arrays; Vertical-cavity surface-emitting laser arrays Item Availability: CD-ROM. INSPEC 4677699 B9407-0170J-019 Doc Type: Conference Paper Title: Area bonding conductive epoxy adhesive preforms for grid array and MCM substrate attach Authors: Bolger, J.C.; Gilleo, K. Affiliation: Merix Corp., Needham, MA, USA Conf. Title: Proceedings 1994 IEEE Multi-Chip Module Conference MCMC-94 (Cat. No.93CH3396-9) p. 77-82 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 xi+149 pp. Country of Publication: USA ISBN: 0 8186 5560 7 CCC: 0 8186 5560 7/94/$03.00 Language: English Conf. Date: 15-17 March 1994 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: Application; Practical; Experimental Abstract: A new type of z-axis epoxy tape adhesive, called an area bond conductive (ABC) adhesive, has been developed under ARPA contract to replace tin-lead solder for surface mounting grid array components. The ABC adhesive tapes contain discrete regions, or 'dots', on pitch down to 0.2 mm, of an electrically conductive epoxy within a high strength, high T/sub g/, epoxy dielectric phase. The adhesives are supplied as die cut preforms, which match the size and bond pad pattern of the component to be attached. The preforms cure at 160-175 degrees C and require no pressure during cure, to yield a shock resistant, void-free area bond to any FR4 or other board surface. This paper presents bond strength, conductivity, dielectric strength, humidity and thermal shock results for daisy chain test circuits and other components attached to FR4 boards. (3 Refs.) Classification: B0170J (Product packaging) Thesaurus: Adhesion; Electric strength; Humidity; Multichip modules; Surface mount technology; Thermal shock Free Terms: Area bonding conductive epoxy adhesive preforms; Grid array; MCM substrate attach; Z-axis epoxy tape adhesive; Surface mounting; Electrically conductive epoxy; Die cut preforms; Bond pad pattern; Void-free area bond; Bond strength; Conductivity; Dielectric strength; Humidity; Thermal shock; Daisy chain test circuits; FR4 boards; 160 To 175 degC Numerical Index: Temperature 4.33E+02 to 4.48E+02 K Item Availability: CD-ROM. INSPEC 4677696 B9407-0170J-016 Doc Type: Conference Paper Title: Laminated memory: a new 3-dimensional packaging technology for MCMs Authors: Tuckerman, D.B.; Bauer, L.-O.; Brathwaite, N.E.; Demmin, J.; Flatow, K.; Hsu, R.; Kim, P.; Lin, C.-M.; Lin, K.; Nguyen, S.; Thipphavong, V. Affiliation: nChip Inc., San Hose, CA, USA Conf. Title: Proceedings 1994 IEEE Multi-Chip Module Conference MCMC-94 (Cat. No.93CH3396-9) p. 58-63 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 xi+149 pp. Country of Publication: USA ISBN: 0 8186 5560 7 CCC: 0 8186 5560 7/94/$03.00 Language: English Conf. Date: 15-17 March 1994 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: New development; Practical Abstract: A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate ('MCM-D'), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests. (17 Refs.) Classification: B0170J (Product packaging); B1265D (Memory circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Economics; Integrated circuit manufacture; Integrated memory circuits; Multichip modules; VLSI Free Terms: Laminated memory; 3D packaging technology; MCMs; Multichip module substrate; Memory chip stacking; High-performance thin-film interconnection substrate; MCM-D; Substrate cost; Memory-intensive design; Assembly cost; MCM cost; High wiring density; Substrate thermal conductivity; Dicing; Adhesive die attach; Wire bonding equipment; Functional memory modules; Thermal shock tests Item Availability: CD-ROM. INSPEC 4673348 B9406-0170J-049 Doc Type: Conference Paper Title: Liquid cooling performance for a 3-dimensional multichip module and miniature heat sink Authors: Vogel, M.R. Affiliation: Sun Microsyst. Inc., Milpitas, CA, USA Conf. Title: Tenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.94CH3413-2) p. 73-7 Publisher: IEEE New York, NY, USA Date: 1994 xi+180 pp. Country of Publication: USA ISBN: 0 7803 1852 8 CCC: 0 7803 1852 8/94/$3.00 Language: English Conf. Date: 1-3 Feb. 1994 Conf. Loc: San Jose, CA, USA Conf. Sponsor: IEEE Treatment: Theoretical/Mathematical; Experimental Abstract: Measured thermal performance is presented for a single phase liquid-cooled module. Tape automated bonded (TAB) thermal test chips and their associated substrates are stacked in a compact, 3-dimensional liquid tight module. A dielectric liquid, polyalphaolefin (PAO) is forced to flow past the active and inactive sides of the TAB chips. At a volumetric flowrate of 0.05 gallons per minute (gpm) and an estimated pressure loss less than 0.5 psi. the measured junction-to-liquid thermal resistance is 2.0 C/W for a 0.50'*0.50'*0.015' thermal test chip. The thermal resistance was also measured for an indirect liquid cooling approach. PAO was used to cool a miniature sink mounted directly to a 0.50'*0.50' heat source. The heat source was used to simulate the thermal characteristics of a chip carrier package. Overall dimensions of the liquid heat sink measured 1.0'*1.0'*0.28'. The measured junction-to-liquid thermal resistance is 0.52 C/W for a flowrate of 0.05 gpm. and for an estimated pressure loss less than 1.0 psi. Numerical computational techniques yielded results which were comparable to the measured thermal resistances for both the 3-dimensional module and the miniature heat sink. Enhanced thermal performance gained by introducing micro encapsulated phase change material to the PAO is estimated for both the 3-dimensional module and the miniature heat sink. (8 Refs.) Classification: B0170J (Product packaging) Thesaurus: Cooling; Heat sinks; Multichip modules; Tape automated bonding; Thermal resistance Free Terms: Liquid cooling performance; 3-Dimensional MCM; 3D multichip module; Miniature heat sink; Thermal performance; Single phase liquid-cooled module; Tape automated bonded chips; TAB thermal test chips; 3D liquid tight module; Dielectric liquid; Polyalphaolefin; Thermal resistance; Indirect liquid cooling; Chip carrier package; Liquid heat sink; Micro encapsulated phase change material Item Availability: CD-ROM. INSPEC 4673345 B9406-0170J-047 Doc Type: Conference Paper Title: Advanced micro air-cooling systems for high density packaging Authors: Gromoll, B. Affiliation: Corp. Res. & Dev., Siemens AG, Erlangen, Germany Conf. Title: Tenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.94CH3413-2) p. 53-8 Publisher: IEEE New York, NY, USA Date: 1994 xi+180 pp. Country of Publication: USA ISBN: 0 7803 1852 8 CCC: 0 7803 1852 8/94/$3.00 Language: English Conf. Date: 1-3 Feb. 1994 Conf. Loc: San Jose, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: Future 3D electronics packaging systems will require micro cooling systems that can be integrated and permit the continued use of air as a coolant. To achieve this, new types of silicon micro heat exchangers were made using an anisotropic etching process. Various heat exchanger configurations and sizes were made using sandwich and stacking techniques. They can be used either as a heat exchanger for direct cooling with compressed air or as a heat pipe and thermosyphon for indirect cooling with fan-blown air. The performance characteristics of the various cooling systems are stated. The micro-heat-pipe can be used for power loss densities of up to 3 W/cm/sup 2/, the direct air cooling up to 15 W/cm/sup 2/ and the thermosyphon up to 25 W/cm/sup 2/. Cooling performances are achieved that are otherwise only possible with liquid cooling. The practical application of the micro cooling system is demonstrated using the example of the Pentium processor. With a power loss of 15 W, the micro cooling system is able to limit the increase in operating temperature to 15 K. The volume of the micro heat exchanger is 2.5 cm/sup 3/ and therefore considerably smaller than that of standard heat sinks. (10 Refs.) Classification: B0170J (Product packaging) Thesaurus: Convection; Cooling; Heat exchangers; Packaging; Temperature distribution Free Terms: Micro air-cooling systems; High density packaging; 3D electronics packaging systems; Si micro heat exchangers; Anisotropic etching process; Heat exchanger configuration; Sandwich/stacking techniques; Heat pipe; Thermosyphon; Fan-blown air; Power loss densities; Pentium processor; Operating temperature increase; 15 W; Si Numerical Index: Power 1.5E+01 W Chemical Index: Si/sur Si/el Item Availability: CD-ROM. INSPEC 4667159 B9406-1265D-023 C9406-5320G-017 Doc Type: Journal Paper Title: Evaluation of a three-dimensional memory cube system Authors: Bertin, C.L.; Perlman, D.J.; Shanken, S.N. Affiliation: IBM Corp., Essex Junction, VT, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 8 p. 1006-11 Date: Dec. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Practical; Experimental Abstract: Silicon cubes consisting of 18-20 1-Mb DRAM chips have been fabricated. In the stacking process, the chips are joined by adhesive to form the cube, interconnected by chip metallization processes, and packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1-Mb DRAM memory modules that normally form the card array. Memory tube operation is verified by testing both original and cube memory cards on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines, and PGA substrate were performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines. (7 Refs.) Classification: B1265D (Memory circuits); B0170J (Product packaging); C5320G (Semiconductor storage) Thesaurus: Adhesion; DRAM chips; Metallisation; Multichip modules; Packaging; Redundancy; Semiconductor storage Free Terms: Three-dimensional memory cube system; Si cubes; DRAM chips; Stacking process; Adhesive; Chip metallization processes; Ceramic pin grid array; PGA substrate; Memory card; Cube interconnect circuitry; Chip transfer metal; Interchip bus lines; Interconnect redundancy; Wiring redundancy; 3D memory system; Dynamic RAMs; 1 Mbit; 18 Mbit; 20 Mbit Numerical Index: Storage capacity 1.0E+06 bit; Storage capacity 1.9E+07 bit; Storage capacity 2.1E+07 bit Item Availability: CD-ROM. INSPEC 4660869 B9406-2240-003 Doc Type: Journal Paper Title: Accelerated life test of Z-axis conductive adhesives Authors: Chang, D.D.; Fulton, J.A.; Ling, H.C.; Schmidt, M.B.; Sinitski, R.E.; Wong, C.P. Affiliation: Eng. Res, Center, AT&T Bell Labs., Princeton, NJ, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 8 p. 836-42 Date: Dec. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Experimental Abstract: The success of coarse-pitch applications of conductive particle-filled adhesives has increased the interest in using such adhesives in fine-pitch applications, such as flip-chip on-board interconnection. Since these materials contain metallic particles to conduct currents in the z-direction (i.e., perpendicular to the plane of circuit board), their propensity for metal migration is a concern. Accelerated temperature, humidity and bias (THB) tests have been applied to a group of materials designed for fine-pitch applications. The accelerated life test conditions were 85 degrees C/85% RH at three different voltages: 10 V, 50 V, and 100 V. The studies were focused on the samples' time-to-failure as well as the associated conduction and failure mechanisms. The test results showed significant metal migrations, and enhanced electric field stresses (10/sup 2/ to 10/sup 4/ V/mm) are proposed as the driving force for failures. (6 Refs.) Classification: B2240 (Microassembly techniques); B0170J (Product packaging); B0170N (Reliability); B0560 (Polymers and plastics (engineering materials science)); B0550 (Composite materials (engineering materials science)) Thesaurus: Adhesion; Conducting polymers; Electromigration; Failure analysis; Filled polymers; Humidity; Leakage currents; Life testing; Microassembling; Packaging; Polymer films Free Terms: Accelerated life test; Z-axis conductive adhesives; Fine-pitch applications; Flip-chip on-board interconnection; Metallic particles; Metal migration; Temperature tests; Humidity tests; Bias tests; Time-to-failure; Failure mechanisms; Electric field stress; Thermoset films; 10 To 100 V; 85 C; 25 To 50 micron Numerical Index: Voltage 1.0E+01 to 1.0E+02 V; Temperature 3.58E+02 K; Size 2.5E-05 to 5.0E-05 m Item Availability: CD-ROM. INSPEC 4660868 B9406-2240-002 Doc Type: Journal Paper Title: An overview and evaluation of anisotropically conductive adhesive films for fine pitch electronic assembly Authors: Chang, D.D.; Crawford, P.A.; Fulton, J.A.; Mcbride, R.; Schmidt, M.B.; Sinitski, R.E.; Wong, C.P. Affiliation: Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 8 p. 828-35 Date: Dec. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: General/Review; Experimental Abstract: Anisotropically conductive adhesive films (ACAFs), which provide electrical as well as mechanical interconnections for fine pitch applications, are discussed. The conductivity of ACAF materials is only in the Z-direction (perpendicular to the plane of the board), and electrical isolation is maintained in the X-Y plane. Currently, at least 15 ACAF materials are commercially available. The authors have developed a methodology for evaluating these materials for their mechanical and electrical properties and interconnection use in the 8 to 15-mil pitch range. In addition they characterized the materials according to their physical properties and cure characteristics. They detail the findings with a comparison of physical form to assembly/cure and final electrical properties. Data from scanning electron microscopy, thermal analysis of the ACAFs, and cure and assembly studies on mixed substrate test vehicles are included. Information on initial electrical testing and long-term reliability testing is given. (4 Refs.) Classification: B2240 (Microassembly techniques); B0560 (Polymers and plastics (engineering materials science)); B0550 (Composite materials (engineering materials science)); B0170J (Product packaging) Thesaurus: Adhesion; Conducting polymers; Electrical conductivity of solids; Filled polymers; Infrared spectra of organic molecules and substances; Mechanical properties of substances; Microassembling; Packaging; Polymer films; Scanning electron microscope examination of materials; Thermal analysis Free Terms: Anisotropically conductive adhesive films; Fine pitch electronic assembly; Mechanical interconnection; Electrical interconnection; Conductivity; ACAF materials; Z-direction conductivity; X-Y plane electrical isolation; Evaluation methodology; Mechanical properties; Electrical properties; Physical properties; Cure characteristics; Scanning electron microscopy; Thermal analysis; Long-term reliability testing; Electrical testing; 8 To 15 mil Numerical Index: Size 2.0E-04 to 3.8E-04 m Item Availability: CD-ROM. INSPEC 4653790 B9406-2570-007 Doc Type: Journal Paper Title: Developing 3D memories Authors: Carson, J.C.; Suer, M.F.; Some, R.R. Affiliation: Irvine Sensors Corp., Costa Mesa, CA, USA Journal: IEEE Micro Vol: 13 Iss: 6 p. 6-7 Date: Dec. 1993 Country of Publication: USA ISSN: 0272-1732 CODEN: IEMIDZ Language: English Treatment: Practical Abstract: Two types of memory chip stacking technologies-full stack and short stack-are in the final stages of development. The full stack places up to 100 ICs in a 'loaf-of-bread' configuration. A typical full stack size is 2.5 cm*1.25 cm*0.65 cm. The short stack puts 4-16 ICs in a 'stack-of-pancakes' configuration. The resultant stack is similar to a thick IC, with typical dimensions of 1.25 cm*0.65 cm*0.025 cm. The two stack form factors support computer memory applications. While the full stack is typically interconnected to the next level of assembly by bump bonding to a substrate or wire bonding into a deep-drawn custom package, the short stack is designed for wirebonding into a deep-drawn custom package, the short stack is designed for wirebonding or TABing (tape automated bonding) into standard packages, SMT, or chip-on-board mounting. (0 Refs.) Classification: B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B2240 (Microassembly techniques) Thesaurus: Integrated memory circuits; Lead bonding; Packaging Free Terms: 3D memories; Memory chip stacking technologies; ICs; Form factors; Computer memory; Substrate; Wire bonding; Tape automated bonding Item Availability: CD-ROM. INSPEC 4647895 B9405-0170J-055 C9405-7410D-095 Doc Type: Conference Paper Title: 3D finite element simulation of the delamination behaviour of a PLCC package in the temperature cycling test Authors: van Gestel, R.; Schellekens, H. Affiliation: Delft Univ. of Technol., Netherlands Conf. Title: 31st Annual Proceedings. Reliability Physics 1993 (Cat. No.93CH3194-8) p. 108-21 Publisher: IEEE New York, NY, USA Date: 1993 x+4111 pp. Country of Publication: USA ISBN: 0 7803 0782 8 CCC: CH3194-8/93/0000-0108$01.00 Language: English Conf. Date: 23-25 March 1993 Conf. Loc: Atlanta, GA, USA Conf. Sponsor: IEEE Treatment: Theoretical/Mathematical Abstract: A full three-dimensional finite-element simulation performed on a model similar to a PLCC plastic package is discussed. In the model three layers of special interface elements were used to simulate the delamination behavior as observed when plastic packages are being stressed by thermal cycles. The interfaces simulated are mould-leadframe leadframe-die, and die-mould. The results of this calculation are used to evaluate the changes of stress inside the package and will be used in combination with test chips capable of measuring die surface stress in further research. (7 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis); B0170N (Reliability); B2570 (Semiconductor integrated circuits); C7410D (Electronic engineering computing); C4185 (Finite element analysis) Thesaurus: Circuit reliability; Delamination; Electronic engineering computing; Failure analysis; Finite element analysis; Packaging; Thermal stress cracking Free Terms: IC package reliability; 3D finite element simulation; Delamination behaviour; Temperature cycling test; PLCC plastic package; Mould-leadframe; Leadframe-die; Die-mould; Changes of stress Item Availability: CD-ROM. INSPEC 4644441 B9405-1130B-021 C9405-7410D-074 Doc Type: Journal Paper Title: High-performance MCM routing Authors: Cho, J.D.; Sarrafzadeh, M.; Sriram, M.; Kang, S.M. Affiliation: Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA Journal: IEEE Design & Test of Computers Vol: 10 Iss: 4 p. 27-37 Date: Dec. 1993 Country of Publication: USA ISSN: 0740-7475 CODEN: IDTCEC CCC: 0740-7475/93/1200-0027$03.00 Language: English Treatment: Theoretical/Mathematical Abstract: The authors describe the multilayer MCM (multichip module) routing problem, and propose an approach for routing high-performance MCMs with the objective of minimizing interconnect delays and crosstalk. They first introduce an approach for rapidly estimating the time-domain response of lossy transmission line trees, and propose a realistic second-order delay model for MCM interconnects. The delay model is used to guide a performance-driven global routing algorithm. Given the 2-D global paths, the next stage is layer assignment. An effective algorithm for constrained layer assignment is developed. Based on the best-known maxcut approximation algorithm (which performs well in practice), a maximal k-color ordering is formulated for minimizing both interlayer and intralayer crosstalk as well as crossings in 3-D MCM substrates. The authors also propose a strategy that exhibits a good tradeoff between circuit performance and design cost, instead of concentrating exclusively on a single objective such as area minimization. (16 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B2210B (Printed circuit layout and design); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits); C7410D (Electronic engineering computing) Thesaurus: Circuit layout CAD; Crosstalk; Multichip modules; Network routing Free Terms: MCM routing; High-performance; Multilayer; Routing problem; Interconnect delays; Crosstalk; Time-domain response; Lossy transmission line trees; Second-order delay model; MCM interconnects; Performance-driven; Global routing algorithm; Layer assignment; Constrained layer assignment; Maxcut approximation; K-color ordering; Circuit performance; Design cost Item Availability: CD-ROM. INSPEC 4598970 B9403-0170J-081 Doc Type: Journal Paper Title: Finite-difference time-domain analysis of pulse propagation in multichip module interconnects Authors: Gribbons, M.; Cangellaris, A.C.; Prince, J.L. Affiliation: Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 5 p. 490-8 Date: Aug. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Theoretical/Mathematical Abstract: The application of the finite-difference-time-domain (FDTD) method to the electromagnetic characterization of multichip-module (MCM) interconnects with perforated (mesh) reference planes is demonstrated. The limitations of the method in finding transmission line propagation characteristics (i.e., characteristic impedance Z/sub 0/ and phase constant beta ) are investigated. An alternative approach for the characterization of MCM interconnects which exploits the capabilities of the FDTD method is suggested. This alternative approach uses the results from the FDTD method to extract the per unit length delay and approximate impulse response of the system. These results can be used to identify the effects of the perforated reference plane on signal propagation. The validity of the TEM approximation for signal propagation in realistic MCM structures is also examined. (13 Refs.) Classification: B0170J (Product packaging); B5240 (Transmission line theory); B0290Z (Other numerical methods) Thesaurus: Electric impedance; Finite difference time-domain analysis; Multichip modules; Transient response; Transmission line theory Free Terms: Packaging; Mesh reference planes; Pulse propagation; Multichip module interconnects; Finite-difference-time-domain; Electromagnetic characterization; Transmission line propagation characteristics; Characteristic impedance; Phase constant; FDTD method; Per unit length delay; Approximate impulse response; Perforated reference plane; Signal propagation; TEM approximation Item Availability: CD-ROM. INSPEC 4592893 B9403-0170J-060 Doc Type: Journal Paper Title: Three-dimensional modeling of multichip module interconnects Authors: Cheung-Wei Lam; Ali, S.M.; Nuytkens, P. Affiliation: Dept. of Electr. Eng., MIT, Cambridge, MA, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 7 p. 699-704 Date: Nov. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Theoretical/Mathematical Abstract: The finite-difference time-domain method with nonuniform grid is applied to the analysis of novel three-dimensional (3D) multichip module (MCM) interconnects. The vertical interconnects involved in this technology consist of small plated via holes defined by a photolithography system. The via dimensions are of the same order as the microstrip and stripline linewidths to reduce the transmission line discontinuities. Two 3D transitions are investigated: 1) microstrip-via-stripline and 2) microstrip-via-90 degrees stripline. Electric field distributions and pulse propagation under the microstrip and the stripline are presented. The scattering parameters for various cases are calculated and compared. Geometrical effects such as different conductor extensions on top of the vias and different hole sizes in the reference plane are also investigated. It is found that the 90 degrees bend structure shows less reflection than the straight one. Designers may introduce such 90 degrees bends intentionally to improve signal transmission. (9 Refs.) Classification: B0170J (Product packaging); B2550G (Lithography); B1310 (Waveguides); B0290Z (Other numerical methods) Thesaurus: Finite difference time-domain analysis; Microstrip lines; Multichip modules; Photolithography; S-parameters Free Terms: Multichip module interconnects; Finite-difference time-domain method; Nonuniform grid; 3D interconnects; Vertical interconnects; Plated via holes; Photolithography system; Microstrip-via-stripline; Microstrip-via-90 degrees stripline; Electric field distributions; Pulse propagation; Scattering parameters; Conductor extensions; Hole sizes Item Availability: CD-ROM. INSPEC 4592891 B9403-2570-037 Doc Type: Journal Paper Title: Characterization of the broadband transmission behavior of interconnections on silicon substrates Authors: Zaage, S.; Groteluschen, E. Affiliation: Lab. fur Informationstech., Hannover Univ., Germany Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 7 p. 686-91 Date: Nov. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Theoretical/Mathematical; Experimental Abstract: In this paper some characteristics of the transmission behavior of interconnections on conductive silicon substrates are presented. With regard to the signal propagation in high-speed digital circuits, the broadband behavior of the lines is of special interest. The characteristic impedance Z/sub C/ and the propagation constant gamma of the lines are determined experimentally by microwave measurements. The influence of the line geometry, the substrate resistivity, and the signal frequency on the transmission behavior are clarified. Based on the results of these measurements, the suitability of the conventional RLC line model for time-domain simulations of the transmission characteristics of interconnections on silicon substrates is clarified. (7 Refs.) Classification: B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B1265 (Digital electronics); B5240 (Transmission line theory) Thesaurus: Digital integrated circuits; Electric impedance; Microstrip lines; Multichip modules; Packaging; Silicon; Substrates; Transmission line theory; VLSI Free Terms: Broadband transmission behavior; Interconnections; Si substrate; Characterization; Conductive substrates; Signal propagation; High-speed digital circuits; Characteristic impedance; Propagation constant; Microwave measurements; Line geometry; Substrate resistivity; Signal frequency; RLC line model; Time-domain simulations; Si Chemical Index: Si/sur Si/el Item Availability: CD-ROM. INSPEC 4592887 B9403-1295-014 C9403-5190-009 Doc Type: Journal Paper Title: 3-D wafer scale architectures for neural network computing Authors: Campbell, M.L.; Toborg, S.T. Affiliation: Aerosp. Corp., Los Angeles, CA, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 7 p. 646-55 Date: Nov. 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Application; Practical Abstract: We introduce a class of massively parallel computer architectures which can be configured to efficiently handle a variety of neural network models. The underlying technology is three-dimensional wafer scale integration (3-D WSI), which provides an ideal medium to construct powerful, compact, and low power hardware tailored for neural network processing. A second generation prototype computer consisting of a 128*128 array of processors formed by stacking 8 CMOS wafers is nearing completion. The performance of this prototype is compared with enhanced architectures configured with special wafer types to accelerate neural network operations. The design of these specialized resources emphasizes the synergy between neural processing functions and the 3-D WSI architecture and packaging. Detailed microcode emulations are used to assess the impact of different algorithm/architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks. Estimated performance for the vision integration network is 2.4 billion connections per second. For the backprop network training algorithm, the performance ranges from 1.1 billion connection updates per second (GCUPS) for a near-term 128*128 prototype up to 53.4 GCUPS for a future 512*512 machine with more extensive neural processing hardware enhancements. (20 Refs.) Classification: B1295 (Neural nets (circuit implementations)); B1265F (Microprocessors and microcomputers); B2570D (CMOS integrated circuits); B0170J (Product packaging); B6140C (Optical information, image and video signal processing); C5190 (Neural net devices); C5220P (Parallel architecture); C5135 (Digital signal processing chips); C5260B (Computer vision and image processing techniques); C5290 (Neural computing techniques) Thesaurus: Backpropagation; CMOS integrated circuits; Digital signal processing chips; Image processing; Neural chips; Packaging; Parallel architectures; VLSI Free Terms: 3D wafer scale architectures; Neural network computing; Massively parallel computer architectures; Three-dimensional wafer scale integration; 3D WSI architecture; Low power hardware; CMOS wafers; Packaging; Microcode emulations; Cooperative vision integration; Multilayer backpropagation; 3D wafer stacks; Backprop network training algorithm Item Availability: CD-ROM. INSPEC 4547196 B9401-1210-020 C9401-7410D-180 Doc Type: Conference Paper Title: Thermal modeling for electrothermal simulation of power devices or circuits Authors: Tounsi, P.; Dorkel, J.-M.; Leturcq, P. Affiliation: Lab. d'Automatique et d'Analyse des Syst., CNRS, Toulouse, France Conf. Title: Fifth European Conference on Power Electronics and Applications (Conf. Publ. No.377) p. 155-60 vol.2 Publisher: IEE London, UK Date: 1993 8 vol. (cx+232+xvi436+xiv+343+xvi483+xxii512+xxii+166+x+205+xii+ 281 pp.) Country of Publication: UK Language: English Conf. Date: 13-16 Sept. 1993 Conf. Loc: Brighton, UK Conf. Sponsor: IEE Treatment: Theoretical/Mathematical Abstract: To perform electrothermal simulation of power devices or circuits, the authors have developed specific thermal simulation tools which only require limited computational time and effort. 3D and transient flow spreading effects in multilayered substrates commonly used in power component packaging as well as in hybrid power circuits are considered. The authors recall the essentials of 3D transient thermal modeling and show how the thermal responses can be made compatible with a general purpose electrical circuit simulator. The concepts are illustrated by carrying out the electrothermal behaviour simulation of a six-chip power VDMOS transistor module. (9 Refs.) Classification: B1210 (Power electronics, supply and supervisory circuits); B2560B (Semiconductor device modelling and equivalent circuits); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing) Thesaurus: Circuit analysis computing; Digital simulation; Equivalent circuits; Hybrid integrated circuits; Modelling; Power electronics; Power integrated circuits; Power transistors; Semiconductor device models; Semiconductor devices; Thermal analysis Free Terms: 3D spreading effects; ESACAP simulator; Electrothermal simulation; Power devices; Thermal simulation tools; Transient flow spreading effects; Multilayered substrates; Power component packaging; Hybrid power circuits; Thermal responses; Power VDMOS transistor module Item Availability: CD-ROM. INSPEC 4536862 B9401-0170E-017 C9401-7480-050 Doc Type: Journal Paper Title: Computer-aided planning systems for integrated electronic and mechanical design Authors: Feldmann, K.; Franke, J. Affiliation: Inst. for Manuf. Autom. & Production Syst., Erlangen Univ., Nurnberg, Germany Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 16 Iss: 4 p. 377-83 Date: June 1993 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/93/$03.00 Language: English Treatment: Practical Abstract: The data processing requirements that arise when integrating housing and circuitry by means of three-dimensional molded interconnection devices (3-D-MIDs) are addressed. An overview of these requirements is given, and promising steps for integrating the functionality of CAD systems for electronic (ECAD) and mechanical (MCAD) applications are described. (13 Refs.) Classification: B0170E (Production facilities and engineering); B0170J (Product packaging); B1130B (Computer-aided circuit analysis and design); C7480 (Production engineering computing); C7410D (Electronic engineering computing) Thesaurus: CAD/CAM; Circuit CAD; Computer aided production planning; Packaging Free Terms: 3D MIDS; Electronic CAD; Mechanical CAD; Data processing requirements; Three-dimensional molded interconnection devices; Functionality; CAD systems; ECAD; MCAD Item Availability: CD-ROM. INSPEC 4534237 B9401-6320-005 Doc Type: Conference Paper Title: An affordable low-profile multifunction structure (ALMS) for an optoelectronic (OE) active array Authors: Newberg, I.L.; Wooldridge, J.J. Affiliation: Hughes Aircraft Co., Los Angeles, CA, USA Conf. Title: 1993 IEEE MTT-S International Microwave Symposium Digest (Cat. No.93CH3277-1) p. 509-12 vol.2 Publisher: IEEE New York, NY, USA Date: 1993 3 vol. (iii+xlv+xlix+1577 pp.) Country of Publication: USA ISBN: 0 7803 1209 0 CCC: CH3277-1/93/0000-0509$01.00 Language: English Conf. Date: 14-18 June 1993 Conf. Loc: Atlanta, GA, USA Conf. Sponsor: IEEE Treatment: Application; Practical Abstract: Three leap-ahead technologies that can be combined into a design to make affordable shared-aperture active array radars are discussed. They are microwave multichip module (MCM) packaging, digital radar, and photonic signal manifolding and true time-delay beamsteering. It is noted that a photonic/MCM/digital radar system will provide a wide bandwidth, shared aperture radar that will be multifunctional and flexible, and one that can be reconfigured for use in a large number of applications. The 3-D design is compact and lightweight for use in conformal and/or embedded structures (smart skins) applications. The use of an all-digital type corporate transmit and receive feed system with a photonic manifold provides a flexible, fault and calibration tolerant configuration. The MCM design will provide subarray wafers that can be manufactured in a cost-effective manner and have high yield, very small size, minimum depth, light weight, and flexibility in mounting and assembly into large arrays, with high reliability and minimum maintainability support requirements. (0 Refs.) Classification: B6320 (Radar equipment, systems and applications); B5270D (Antenna arrays); B0170J (Product packaging) Thesaurus: Active antennas; Microwave antenna arrays; Multichip modules; Radar equipment Free Terms: Affordable low-profile multifunction structure; Shared-aperture active array radars; Microwave multichip module; Digital radar; Photonic signal manifolding; Time-delay beamsteering; Embedded structures; Photonic manifold; Calibration tolerant configuration; Subarray wafers; Yield; Depth; Weight; Maintainability support requirements Item Availability: CD-ROM. INSPEC 4503596 B9311-0170J-018 Doc Type: Conference Paper Title: Three dimensional hybrid wafer scale integration using the GE high density interconnect technology Authors: Wojnarowski, R.J.; Fillion, R.A.; Gorowitz, B.; Saia, R. Affiliation: Gen. Electr. Co., Schenectady, NY, USA Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 309-17 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A three-dimensional multichip technology is discussed. It provides solutions to the interconnect and packaging problems associated with very high density requirements of large distributed processing systems and large solid-state memory systems. The technical approach involves an extension of the 2D multichip module (MCM) circuits fabricated with the high-density-interconnect (HDI) overlay technology. These are then stacked and interconnected with a modified version of the 2D HDI interconnect process applied to the side edges of the stack. Test structures and a stack of function circuit circuits are fabricated and tested. The features of this approach, a description of the process, and the results of tests on the demonstration vehicles are presented. (6 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits) Thesaurus: Hybrid integrated circuits; Integrated circuit technology; Multichip modules; VLSI Free Terms: 3D hybrid WSI; HDI overlay technology; 3D MCM; Wafer scale integration; High density interconnect technology; Three-dimensional multichip technology; Interconnect; Packaging; Very high density requirements; Large distributed processing systems; Solid-state memory systems; Multichip module Item Availability: CD-ROM. INSPEC 4503571 B9311-1295-023 C9311-5290-046 Doc Type: Conference Paper Title: 3D wafer stack neurocomputing Authors: Campbell, M.L.; Toborg, S.T.; Taylor, S.L. Affiliation: Hughes Res. Lab., Malibu, CA, USA Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 67-74 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A family of massively parallel multiple-single-instruction multiple-data (MSIMD) architectures which can be configured to efficiently handle a variety of different neural network models is introduced. The underlying technology is three dimensional wafer scale integration (3D WSI), which provides an ideal medium for constructing low-power hardware tailored for neural network processing. The performance of this prototype is compared with that of enhanced architectures configured with special wafer types to accelerate neural network operations. The design emphasizes the synergy between neural processing functions and the 3D WSI architecture and packaging. Detailed microcode emulations are used to access the impact of different algorithms and architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks. (6 Refs.) Classification: B1295 (Neural nets (circuit implementations)); C5290 (Neural computing techniques); C5220P (Parallel architecture); C5190 (Neural net devices) Thesaurus: Backpropagation; Feedforward neural nets; Neural chips; Parallel architectures; VLSI Free Terms: Massively parallel architectures; MSIMD; 3D wafer stack neurocomputing; Multiple-single-instruction multiple-data; Neural network models; Three dimensional wafer scale integration; Neural processing functions; Microcode emulations; Cooperative vision integration; Multilayer backpropagation Item Availability: CD-ROM. INSPEC 4493530 B9311-2220J-005 C9311-7410D-086 Doc Type: Conference Paper Title: A fast multilayer general area router for MCM designs Authors: Khoo, K.-Y.; Cong, J. Affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA Conf. Title: EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0) p. 292-7 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xviii+765 pp. Country of Publication: USA ISBN: 0 8186 2780 8 CCC: 0 8186 2780 8/92/$3.00 Language: English Conf. Date: 7-10 Sept. 1992 Conf. Loc: Hamburg, Germany Conf. Sponsor: IEEE; Gesellschaft fur Inf.; ACM; AFCET; BCS; CEPS; EDAC Treatment: Practical Abstract: The authors report on the development of an efficient multilayer general area router as an alternative to the three-dimensional (3-D) maze router for solving the multilayer multichip module (MCM) routing problem. The router, named SLICE, is independent of net ordering, requires much shorter computation time, and uses fewer vias. A key step in the router is to compute a maximum non-crossing bipartite matching, which is solved optimally in O(n log n) time where n is the number of possible connections. The router was tested on a number of examples, including two MCM designs. Compared to a 3-D maze router, SLICE is four times faster and uses 28% fewer vias. SLICE can successfully produce solutions for large MCM routing examples where 3-D maze routers fail due to insufficient memory. (15 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging); C7410D (Electronic engineering computing) Thesaurus: Circuit layout CAD; Multichip modules Free Terms: Fast multilayer general area router; MCM designs; Multilayer multichip module; SLICE; Bipartite matching; 3-D maze router Item Availability: CD-ROM. INSPEC 4488176 B9311-1130B-007 C9311-7410D-039 Doc Type: Conference Paper Title: Three dimensional circuit oriented electromagnetic modeling for VLSI interconnects Authors: Heeb, H.; Ruehli, A.E.; Bracken, J.E.; Rohrer, R.A. Affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA Conf. Title: IEEE 1992 International Conference on Computer Design: VLSI in Computers and Processors. ICCD '92 (Cat. No.92CH3189-8) p. 218-21 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xvii+605 pp. Country of Publication: USA ISBN: 0 8186 3110 4 CCC: 1063-6404/92/$3.00 Language: English Conf. Date: 11-14 Oct. 1992 Conf. Loc: Cambridge, MA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A general approach for modeling 3-D layout geometries is presented. In particular, the partial-element equivalent circuit (PEEC) technique has been used successfully to model interconnect structures for chips and packages. The technique, which is circuit based, permits the electrical modeling of arbitrary 3-D geometries and allows 3-D transmission line properties to be analyzed. Recently, the technique has been extended to include retardation and dielectric layers. The authors have experimented with the use of the asymptotic waveform evaluation (AWE) approach to speed up the solution of the resulting circuit equations. (10 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B5230 (Electromagnetic compatibility and interference); C7410D (Electronic engineering computing) Thesaurus: Circuit analysis computing; Circuit layout CAD; Electromagnetic interference; Packaging; VLSI Free Terms: 3D circuit oriented EM modelling; VLSI interconnects; 3-D layout geometries; Partial-element equivalent circuit; Chips; Packages; Electrical modeling; Retardation; Dielectric layers; Asymptotic waveform evaluation Item Availability: CD-ROM. INSPEC 4474577 C9310-4230M-011 Doc Type: Conference Paper Title: Hierarchical shuffle-exchange and de Bruijn networks Authors: Cypher, R.; Sanz, J.L.C. Affiliation: IBM Almaden Res. Center, San Jose, CA, USA Conf. Title: Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing (Cat. No.92TH0492-9) p. 491-6 Publisher: IEEE New York, NY, USA Date: 1992 xiii+527 pp. Country of Publication: USA ISBN: 0 8186 3200 3 CCC: 0 8186 3200 3/92/$3.00 Language: English Conf. Date: 1-4 Dec. 1992 Conf. Loc: Arlington, TX, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: The authors present two new classes of interconnection networks for SIMD (single-instruction multiple-data) computers, namely, the hierarchical shuffle-exchange (HSE) and hierarchical de Bruijn (HdB) networks. These networks are efficient in implementing a wide range of algorithms, including all of those in the classes ascend and descend. The networks are highly regular and scalable, and well-suited to VLSI implementation. In addition, they can be adjusted to match the pin limitations imposed by the packaging technology. The authors compare the HSE and HdB networks with hypercube, 2-D mesh, 3-D mesh, shuffle-exchange, hypernet, de Bruijn, and cube-connected cycles networks. The HSE and HdB networks are shown to have advantages in terms of regularity, scalability, and performance. (27 Refs.) Classification: C4230M (Multiprocessor interconnection); C5220P (Parallel architecture); C5440 (Multiprocessing systems); C5470 (Performance evaluation and testing) Thesaurus: Hypercube networks; Parallel processing; Performance evaluation Free Terms: Hierarchical shuffle exchange networks; De Bruijn networks; SIMD; Single-instruction multiple-data; VLSI implementation; Packaging; Hypercube; 2-D mesh; 3-D mesh; Shuffle-exchange; Hypernet; Cube-connected cycles networks; Regularity; Scalability; Performance Item Availability: CD-ROM. INSPEC 4432497 B9308-0170J-008 C9308-5490-001 Doc Type: Conference Paper Title: Heat transfer in a low aspect ratio horizontal enclosure for laptop computer application Authors: Ortega, A.; Lall, B.S.; Chicci, J.; Aghazadeh, M.; Kiang, B. Affiliation: Dept. of Aerosp. & Mech. Eng., Arizona Univ., Tucson, AZ, USA Conf. Title: Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.93CH3226-8) p. 42-9 Publisher: IEEE New York, NY, USA Date: 1993 x+214 pp. Country of Publication: USA ISBN: 0 7803 0863 8 CCC: 0 7803 0863 8/93/$3.00 Language: English Conf. Date: 2-4 Feb. 1993 Conf. Loc: Austin, TX, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: Experiments were performed to characterize the combined conduction, convection, and radiation heat transfer from a horizontal component board in a shallow horizontal enclosure. Measurements were made in both a simulated enclosure with well controlled thermal boundary conditions and an actual electronic enclosure. Comparison was made with simulated results using a commercial three dimensional conduction code with heat transfer coefficient boundary conditions and two simple one-dimensional models which ignore z-direction conduction in the board. The one-dimensional models compared well with the three-dimensional simulations. Agreement between experimental and simulation results was excellent. The results point out the importance of thermal radiation in the enclosure. The results show that the magnitude of the heat transfer coefficient used in the predictive model does not have to be known extremely accurately to predict maximum board temperatures with good accuracy. (17 Refs.) Classification: B0170J (Product packaging); C5490 (Other aspects of analogue and digital computers); C5430 (Microcomputers) Thesaurus: Convection; Heat conduction; Heat radiation; Packaging; Portable computers Free Terms: Aspect ratio; Horizontal enclosure; Laptop computer application; Conduction; Convection; Radiation heat transfer; Horizontal component board; Thermal boundary conditions; Three dimensional conduction code; Boundary conditions; One-dimensional models; Thermal radiation; Maximum board temperatures Item Availability: CD-ROM. INSPEC 4432492 B9308-2220J-002 Doc Type: Conference Paper Title: Analysis and measurement of thermal resistance in a 3-dimensional silicon multichip module populated with assembly test chips Authors: Sweet, J.N.; Peterson, D.W.; Chu, D.; Bainbridge, B.L.; Gassman, R.A.; Reber, C.A. Affiliation: Sandia Nat. Lab., Alburquerque, NM, USA Conf. Title: Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.93CH3226-8) p. 1-7 Publisher: IEEE New York, NY, USA Date: 1993 x+214 pp. Country of Publication: USA ISBN: 0 7803 0863 8 CCC: 0 7803 0863 8/93/$3.00 Language: English Conf. Date: 2-4 Feb. 1993 Conf. Loc: Austin, TX, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: A three-dimensional multichip module (MCM) using a silicon-on-silicon architecture has been constructed to evaluate the thermal performance of various design schemes. The module has three planes of die, each populated of four assembly test chips (ATCs). Each chip has an array of 48 temperature sensing diodes, which are used to map the temperature distribution across the chip surface. The design and construction of the module are discussed and the calibration of the diodes are reviewed. Experimental results are presented for the top surface temperature distribution with the bottom substrate connected to a heat sink. These results are compared to those from a full finite element calculation as well as to results using more approximate thermal analysis tools. (8 Refs.) Classification: B2220J (Hybrid integrated circuits); B7320R (Thermal variables measurement); B7230 (Sensing devices and transducers) Thesaurus: Calibration; Electric sensing devices; Multichip modules; Thermal resistance measurement Free Terms: 3D module; Thermal resistance; Multichip module; Assembly test chips; Silicon-on-silicon architecture; Thermal performance; Temperature sensing diodes; Temperature distribution; Chip surface; Calibration; Heat sink; Finite element calculation; Thermal analysis tools Item Availability: CD-ROM. INSPEC 4416265 B9307-1130B-025 C9307-7410D-056 Doc Type: Journal Paper Title: A fast multilayer general area router for MCM designs Authors: Khoo, K.-Y.; Cong, J. Affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA Journal: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing Vol: 39 Iss: 11 p. 841-51 Date: Nov. 1992 Country of Publication: USA ISSN: 1057-7130 CODEN: ICSPE5 CCC: 1057-7130/92/$03.00 Language: English Treatment: Practical; Theoretical/Mathematical Abstract: An efficient multi layer general area router is developed as an alternative to the 3-D maze router for solving the multi-layer multichip module (MCM) routing problem. The router, named SLICE, is independent of net ordering, requires much shorter computation time, and uses fewer vias. A key step is to compute a maximum noncrossing bipartite matching, which is solved optimally in O(n log n) time where n is the number of possible connections. The router was tested on a number of examples, including two MCM designs from MCC. The total wirelength used by SLICE is only a few percent away from the optimal on average. Compared with a 3-D maze router, SLICE is six times faster and uses 29% fewer vias. Another feature of SLICE is that it works on only a 'thin slice' of a two-layer routing grid at a time, so it can produce solutions for large MCM routing examples where 3-D maze routers fail due to insufficient memory. (18 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B0170J (Product packaging); C7410D (Electronic engineering computing) Thesaurus: Circuit layout CAD; Multichip modules; Network routing Free Terms: Packaging; Multilayer general area router; MCM designs; Multichip module; SLICE; Maximum noncrossing bipartite matching; Two-layer routing grid Item Availability: CD-ROM. INSPEC 4399585 B9306-1130B-069 C9306-7410D-141 Doc Type: Conference Paper Title: Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics Authors: Nabors, K.; White, J. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Conf. Title: Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3) p. 710-15 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xxvi+721 pp. Country of Publication: USA ISBN: 0 8186 2822 7 CCC: 0738-100X/92/$3.00 Language: English Conf. Date: 8-12 June 1992 Conf. Loc: Anaheim, CA, USA Conf. Sponsor: IEEE; ACM SIGDA Treatment: Theoretical/Mathematical; Experimental Abstract: The new three-dimensional capacitance calculation program FASTCAP2 is described. Like the earlier program FASTCAP, FASTCAP2 is based on a multipole-accelerated algorithm that is efficient enough to allow three-dimensional capacitance calculations to be part of an iterative design process. FASTCAP2 differs from FASTCAP in that it was able to analyze problems with multiple-dielectrics, thus extending the applicability of the multiple-accelerated approach to a wider class of integrated circuit interconnect and packaging problems. (10 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B1190 (Other and miscellaneous topics in circuit theory); C7410D (Electronic engineering computing) Thesaurus: Capacitance; Circuit analysis computing Free Terms: Equivalent charge; Panel potentials; Conformal dielectrics; Three-dimensional capacitance calculation program; FASTCAP2; FASTCAP; Multipole-accelerated algorithm; Iterative design process; Multiple-dielectrics; Integrated circuit interconnect Item Availability: CD-ROM. INSPEC 4394909 B9306-0170J-018 Doc Type: Conference Paper Title: Trends in cooling technology for high-density packaging Authors: Gromoll, B. Affiliation: Siemens AG, Erlangen, Germany Conf. Title: CompEuro 1992 Proceedings. Computer Systems and Software Engineering (Cat. No.91CH3121-1) p. 304-9 Editors: Dewilde, P.; Vandewalle, J. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xviii+717 pp. Country of Publication: USA ISBN: 0 8186 2760 3 CCC: 0 8186 2760 3/92$03.00 Language: English Conf. Date: 4-8 May 1992 Conf. Loc: The Hague, Netherlands Conf. Sponsor: IEEE Treatment: General/Review Abstract: A general look at the development of cooling systems for multichip modules over the last few years reveals a clear increase in the levels of power dissipation. Heat transfer and cooling methods for multichip modules are considered. The extremely high demands placed on cooling systems are leading to increasingly cost-intensive technical solutions. Microcooling systems must be capable of integration in order to cool the 3D computer structures of the future. A microcooler produced in Si etched technology is presented as the foundation of this type of cooling system. (15 Refs.) Classification: B0170J (Product packaging) Thesaurus: Cooling; Multichip modules Free Terms: Heat transfer; High-density packaging; Cooling systems; Multichip modules; Power dissipation; Cost-intensive technical solutions; Integration; 3D computer structures; Microcooler; Si etched technology Chemical Index: Si/int Si/el Item Availability: CD-ROM. INSPEC 4394098 B9306-0170J-014 Doc Type: Journal Paper Title: Three-dimensional interconnect analysis using partial element equivalent circuits Authors: Heeb, H.; Ruehli, A.E. Affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA Journal: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications Vol: 39 Iss: 11 p. 974-82 Date: Nov. 1992 Country of Publication: USA ISSN: 1057-7122 CODEN: ITCAEX CCC: 1057-7122/92/$03.00 Language: English Treatment: Theoretical/Mathematical Abstract: Two extensions to the partial element equivalent circuit (PEEC) approach for interconnect modeling are presented. First, retardation, the effect of the finite speed of electromagnetic interactions, is included. Second, PEEC is extended to include a circuit model of finite-size homogeneous dielectrics. It is shown that the retarded PEEC formulation with the new dielectric model is equivalent to a full-wave solution of Maxwell's equation. Since they can be combined with linear and nonlinear circuits, the resulting models are more flexible than existing full-wave solvers. (23 Refs.) Classification: B0170J (Product packaging); B1150F (Distributed linear networks) Thesaurus: Distributed parameter networks; Equivalent circuits; Linear network analysis; Packaging Free Terms: 3D interconnect modelling; Interconnect analysis; Partial element equivalent circuits; Electromagnetic interactions; Circuit model; Finite-size homogeneous dielectrics Item Availability: CD-ROM. INSPEC 4394095 B9306-0170J-012 Doc Type: Journal Paper Title: Multipole-accelerated capacitance extraction algorithms for 3-D structures with multiple dielectrics Authors: Nabors, K.; White, J. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Journal: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications Vol: 39 Iss: 11 p. 946-54 Date: Nov. 1992 Country of Publication: USA ISSN: 1057-7122 CODEN: ITCAEX CCC: 1057-7122/92/$03.00 Language: English Treatment: Theoretical/Mathematical Abstract: The authors describe how to extend the multiple-accelerated boundary-element method for 3-D capacitance computation to the case where conductors are embedded in an arbitrary piecewise-constant dielectric medium. Results are presented to demonstrate that the method is accurate, has nearly linear computational growth, and can be nearly two orders of magnitude faster than the standard boundary-element method based on matrix factorization. (14 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis) Thesaurus: Boundary-elements methods; Capacitance; Packaging Free Terms: 3D structures; Multipole accelerated BEM; IC interconnects; IC packaging; Capacitance extraction algorithms; Multiple dielectrics; Boundary-element method; Piecewise-constant dielectric medium Item Availability: CD-ROM. INSPEC 4391018 B9306-0170J-006 Doc Type: Conference Paper Title: Three dimensional circuit oriented electromagnetic modeling for VLSI packaging Authors: Ruehli, A.; Heeb, H. Affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA Conf. Title: IEEE Antennas and Propagation Society International Symposium. 1992 Digest. Held in Conjuction with: URSI Radio Science Meeting and Nuclear EMP Meeting (Cat. No.92CH3178-1) p. 1256 vol.3 Publisher: IEEE New York, NY, USA Date: 1992 4 vol. xii+2324 pp. Country of Publication: USA ISBN: 0 7803 0730 5 Language: English Conf. Date: 18-25 July 1992 Conf. Loc: Chicago, IL, USA Conf. Sponsor: IEEE; Motorola; Andrew Corp.; Cray Res.; Illinois Inst. Technol.; Northwestern Univ.; Univ. Illinois Treatment: Theoretical/Mathematical Abstract: Summary form only given. Circuit-oriented approaches for the solution of interconnect problems were considered. Issues for partial element equivalent circuit modeling, such as retardation and dielectrics, were examined. This corresponds to a full wave electromagnetic solution of the problem. A further issue discussed was potential circuit solver methods for the solution of these problems. The solution of these problems is very time consuming due to the couplings, and exact as well as approximate solution techniques may be appropriate in some cases. (0 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits) Thesaurus: Equivalent circuits; Packaging; Semiconductor process modelling; VLSI Free Terms: 3D circuit oriented EM modeling; VLSI packaging; Interconnect problems; Partial element equivalent circuit modeling; Retardation; Dielectrics; Full wave electromagnetic solution; Circuit solver methods Item Availability: CD-ROM. INSPEC 4359016 B9304-0170J-040 Doc Type: Conference Paper Title: Effects of die pad anchoring on package interfacial integrity Authors: Nguyen, L.T.; Michael, M.M. Affiliation: National Semiconductor Corp., Santa Clara, CA, USA Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 930-8 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0930$03.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Theoretical/Mathematical Abstract: The effects of anchoring the die pad to the epoxy molding compound to improve the package interfacial integrity are addressed. The designs considered varied from simple circular holes dispersed at the four corners of the die pad to longer slots distributed along the periphery of the die. 3-D finite element models were constructed to simulate the residual stress profiles within the various molded configurations. Interfacial delamination was artificially induced at selected locations of the die pad by nodal decoupling. The simulation results were compared with acoustic tomograph scans of the packages to assess any correlation between the predicted high stress profiles and the extent of delamination observed. The introduction of an anchor in the die pad provided various degrees of stress relief to the silicon die, depending on the anchor geometry. Although the effects were localized, the ensuing stress reduction was sufficient in some cases to avoid the initiation of delamination. Finite-element results also pinpointed other areas of high stress concentration, which acted as potential sites where delamination could initiate and propagate. Based on these results, design criteria were formulated to dictate the most efficient pattern of holes and slots that would provide the best anchoring properties to the molding compound. (19 Refs.) Classification: B0170J (Product packaging); B0290T (Finite element analysis) Thesaurus: Delamination; Finite element analysis; Packaging; Simulation; Stress analysis Free Terms: 3D FEM models; Die pad anchoring; Package interfacial integrity; Epoxy molding compound; Finite element models; Stress profiles; Delamination; Nodal decoupling; Simulation; Acoustic tomograph scans; Anchor geometry; Stress reduction; Design criteria; Si Chemical Index: Si/sur Si/el Item Availability: CD-ROM. INSPEC 4348140 B9303-0170J-091 Doc Type: Conference Paper Title: An overview of elastomeric conductive polymer interconnection materials and their use in MCM technology Authors: Fulton, J.A.; Chang, D.D.; Nis, J.R.; Schmidt, M.B. Affiliation: AT&T Bell Labs., Princeton, NJ, USA Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 473-80 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0473$03.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Application; General/Review Abstract: A family of anisotropically conducting metal-filled polymer composites that are representative of ACPF (anisotropically conducting polymer film) has been developed. These composites are collectively referred to as elastomeric conductive polymer interconnection (ECPI) materials. The ECPI materials are metal-polymer composites with conduction isolated to the thin (or Z) direction, as are all ACPF materials. These materials offer unique advantages over more conventional technologies used for module attachment, high density connectors, socketing, and device testing. ECPI materials are well suited to interconnecting pad-grid arrays and, because of their electrical properties and mechanical compliance, they can accommodate short-range surface variations of several mils and transmit high-frequency signals without distortion, and their through-contact resistance is low. In general, ECPI needs only the application of pressure to give interconnection, but a group of design criteria was developed to assure optimal performance. The ECPI structure is discussed, the electrical and mechanical properties of typical ECPI interconnections are described, and design guidelines for using ECPI in connector and testing applications are summarized. (6 Refs.) Classification: B0170J (Product packaging); B0560 (Polymers and plastics (engineering materials science)); B2180E (Connectors) Thesaurus: Conducting polymers; Elastomers; Electric connectors; Filled polymers; Multichip modules; Packaging Free Terms: Elastomeric conductive polymer; Interconnection materials; MCM technology; Metal-filled polymer composites; ECPI materials; Module attachment; High density connectors; Pad-grid arrays; Electrical properties; Mechanical compliance; High-frequency signals; Design criteria; Testing applications Item Availability: CD-ROM. INSPEC 4348122 B9303-2570-031 Doc Type: Conference Paper Title: The 3D stack in short form (memory chip packaging) Authors: Minahan, J.A.; Pepe, A.; Some, R.; Suer, M. Affiliation: Irvine Sensors Corp., Costa Mesa, CA, USA Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 340-4 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0340$03.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: A novel form of 3D high-density stack, called a short stack, has been built and tested. One version of the short stack allowed accurate measurement of the T-connect resistance, approximately=0.025 ohms, while a second version was designed to provide four memory chips stacked for use in a low headroom application that incorporated the 3D technology with the high-density interconnect multichip approach. (0 Refs.) Classification: B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B1265D (Memory circuits) Thesaurus: Integrated circuit technology; Integrated memory circuits; Packaging Free Terms: Stacked memory chips; 3D high-density stack; Short stack; T-connect resistance; Low headroom application Item Availability: CD-ROM. INSPEC 4348107 B9303-2220J-014 Doc Type: Conference Paper Title: Multichip module connector evaluation at Unisys Authors: Kuntz, R.J. Affiliation: Unisys Corp., Rancho Bernardo, CA, USA Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 252-7 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0252$3.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: Unisys Corporation has been pursuing a course towards high pin count multichip modules (MCMs) for several years. The module development program includes an effort to evaluate and test the connectors required to interconnect these modules. Central to this effort is the Z-AXIS Interconnect Program, which concentrates on the pinless (or pad array) connectors. The studies and testing so far indicate that a Z-AXIS connector like the Fuzz Button is a viable approach for a pad array interconnection of an MCM. The flatness and structural requirements have been studied and determined to be manageable. Testing of buttons has demonstrated that initially buttons can be made to work. Related experience with button connections has been good. (1 Refs.) Classification: B2220J (Hybrid integrated circuits); B2180E (Connectors); B0170J (Product packaging) Thesaurus: Electric connectors; Multichip modules Free Terms: Pinless connectors; Unisys; High pin count multichip modules; Connectors; Z-AXIS Interconnect Program; Pad array; Fuzz Button; Structural requirements; Button connections Item Availability: CD-ROM. INSPEC 4341764 B9303-0170J-053 Doc Type: Conference Paper Title: Solder joint reliability of a thin small outline package (TSOP) Authors: Lau, J.; Golwalkar, S.; Boysan, P.; Surratt, R.; Rice, D.; Forhringer, R.; Erasmus, S. Affiliation: Hewlett-Packard Co. Palo Alto, CA, USA Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 519-32 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0519$03.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical; Experimental Abstract: The reliability of 0.5 mm pitch, 32-pin thin small outline package (TSOP) solder joints was studied by experimental temperature cycling and a cost-effective 3D nonlinear finite element analysis. Temperature cycling results were presented as a Weibull distribution, and an acceleration factor was established for predicting the failure rate at operating conditions. The thermal fatigue life of the corner solder joints was estimated based on the calculated plastic strain the Coffin-Manson law, and isothermal fatigue data on solders. A correlation between the experimental and analytical results was also made. Failure analysis of the solder joints was performed using scanning electron microscopy and an optical method. A quantitative comparison between the Type-I and Type-II TSOP solder joints is presented. (24 Refs.) Classification: B0170J (Product packaging); B0170N (Reliability); B0170E (Production facilities and engineering); B2210D (Printed circuit manufacture) Thesaurus: Environmental testing; Failure analysis; Fatigue testing; Packaging; Printed circuit manufacture; Reliability; Scanning electron microscopy; Soldering; Surface mount technology; Thermal stress cracking Free Terms: Failure analysis; Solder joint reliability; Type-I TSOP; Thin small outline package; TSOP; Temperature cycling; 3D nonlinear finite element analysis; Weibull distribution; Acceleration factor; Failure rate; Thermal fatigue life; Corner solder joints; Calculated plastic strain; Coffin-Manson law; Isothermal fatigue data; Scanning electron microscopy; Optical method; Type-II TSOP; Solder joints; 0.5 Mm Numerical Index: Distance 5.0E-04 m Item Availability: CD-ROM. INSPEC 4296833 B9301-0170J-049 Doc Type: Conference Paper Title: Thermal characterization of an alumina ceramic MCM with conductive slugs Authors: Kozarek, R.L.; Steicher, E.T. Affiliation: Aloca Lab., Aloca Center, PA, USA Conf. Title: InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM III (Cat. No.92CH3096-5) p. 262 Publisher: IEEE New York, NY, USA Date: 1992 xii+292 pp. Country of Publication: USA ISBN: 0 7803 0503 5 CCC: CH3096-5/92/0000-0262$01.00 Language: English Conf. Date: 5-8 Feb. 1992 Conf. Loc: Austin, TX, USA Conf. Sponsor: IEEE; ASME; Int. Soc. Hybrid Microelectron.; NIST Treatment: Theoretical/Mathematical; Experimental Abstract: Summary form only given. The authors describe the thermal characterization of a high-performance air-cooled MCM (multichip module) packaging technology that uses high thermal conductivity slug inserts with a cofired alumina/tungsten ceramic body. The slugs function as a heat conduction medium from the chips to a heat sink. The authors examine the performance limitations and tradeoffs of various material options for the package, such as slug, die attach, and heat sink attach materials. They also examine the effect of different operating conditions such as varying power density between chips and external cooling with different types of air-cooled heat sinks for tangential flow or impingement flow as a function of the air flow rate. A combination of modeling and experimental measurements were used to thermally characterize a four-chip MCM test vehicle. This study illustrates the need to use measurements to refine detailed 3D finite-element models to achieve accurate thermal predictions for the wide variety of conditions and materials needed to characterize a packaging technology. (0 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B0290T (Finite element analysis) Thesaurus: Alumina; Ceramics; Cooling; Finite element analysis; Heat sinks; Modelling; Multichip modules; Thermal analysis Free Terms: 3D FEM; Alumina ceramic MCM; Conductive slugs; Thermal characterization; Air-cooled MCM; Multichip module; Packaging technology; Slug inserts; Die attach; Heat sink attach materials; Power density; External cooling; Air-cooled heat sinks; Air flow rate; Modeling; Finite-element models; Al/sub 2/O/sub 3/; W; Cofired Al/sub 2/O/sub 3/-W ceramic Chemical Index: Al2O3/bin Al2/bin Al/bin O3/bin O/bin; W/el; Al2O3W/ss Al2O3/ss Al2/ss Al/ss O3/ss O/ss W/ss Item Availability: CD-ROM. INSPEC 4288299 B9301-2220J-005 C9301-5440-006 Doc Type: Journal Paper Title: Ultra-Dense: an MCM-based 3-D digital signal processor Authors: Segelken, J.M.; Wu, L.J.; Lau, M.Y.; Tai, K.L.; Shively, R.R.; Grau, T.G. Affiliation: AT&T Bell Labs., Murray Hill, NJ, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 15 Iss: 4 p. 438-43 Date: Aug. 1992 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/92/$03.00 Language: English Treatment: General/Review; Practical; Product review Abstract: The DSP3 Multiprocessor Project has produced a multi-GFLOP machine that is applicable to a variety of signal processing and pattern recognition problems. A companion program, the Ultra-Dense Project, is utilizing silicon-on-silicon multichip module (MCM) technology and innovative advanced packaging and physical design to achieve a parallel three-dimensional digital signal processor based on the DSP3. The authors present an overview and outline systems architecture the micro-interconnect technology (Si-on-Si MCM), and advances in physical design and packaging technology leading to an ultra-dense project demonstration. (4 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging); C5440 (Multiprocessing systems); C5220P (Parallel architecture) Thesaurus: Multichip modules; Packaging; Parallel architectures; Parallel machines Free Terms: Parallel processors; 3-D digital signal processor; DSP3; Multiprocessor Project; Multi-GFLOP machine; Ultra-Dense Project; Overview; Systems architecture; Micro-interconnect technology; Si-on-Si MCM; Physical design; Packaging technology; Ultra-dense project demonstration; Si-Si modules Chemical Index: Si-Si/int Si/int Si/el Item Availability: CD-ROM. INSPEC 4275750 B9212-2220J-025 Doc Type: Conference Paper Title: A high-speed multi-dielectric capacitance-extraction algorithm for MCM interconnects Authors: Le Coz, Y.L.; Iverson, R.B. Affiliation: Dept. of Electr.-Comput.-Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: Proceedings. 1992 IEEE Multi-Chip Module Conference MCMC-92 (Cat. No.92CH3124-5) p. 86-9 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xii+181 pp. Country of Publication: USA ISBN: 0 8186 2725 5 CCC: 0 8186 2725 5/92$03.00 Language: English Conf. Date: 18-20 March 1992 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: The authors report an extension of a stochastic algorithm for capacitance extraction in complex two- and three-dimensional multidielectric structures. The algorithm has applications in the area of circuit modeling of multichip modules. The extension is in the form of a simple probability rule that depends on the ratio of electric permittivities across dielectric interfaces. Computational results are presented for a two-dimensional cross-section of a wire running over a dielectric and ground plane. Results are also presented for a three-dimensional interconnect via partially embedded in a dielectric over a ground plane. All computations were performed on a personal computer. Execution times were nominally five minutes for statistical errors ranging from one to ten percent, depending on dimensionality and value of the dielectric constant. An extraction methodology was devised for large conductor arrays based on superimposing a geometrical hashing grid. (3 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging); B2130 (Capacitors) Thesaurus: Capacitance; Hybrid integrated circuits; Metallisation; Modules Free Terms: 2D structures; 3D structures; Multi-dielectric capacitance-extraction algorithm; MCM interconnects; Stochastic algorithm; Multidielectric structures; Circuit modeling; Multichip modules; Probability rule; Electric permittivities; Dielectric interfaces; Ground plane; Statistical errors; Large conductor arrays; Geometrical hashing grid Item Availability: CD-ROM. INSPEC 4251147 B9211-0170J-055 C9211-7410D-112 Doc Type: Journal Paper Title: Fast capacitance extraction of general three-dimensional structures Authors: Nabors, K.; Kim, S.; White, J. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Journal: IEEE Transactions on Microwave Theory and Techniques Vol: 40 Iss: 7 p. 1496-506 Date: July 1992 Country of Publication: USA ISSN: 0018-9480 CODEN: IETMAB CCC: 0018-9480/92/$03.00 Language: English Treatment: Theoretical/Mathematical Abstract: K. Nabors and J. White (1991) presented a boundary-element-based algorithm for computing the capacitance of three-dimensional m-conductor structures whose computational complexity grows nearly as mn, where n is the number of elements used to discretize the conductor surfaces. In that algorithm, a generalized conjugate residual iterative technique is used to solve the n*n linear system arising from the discretization, and a multipole algorithm is used to compute the iterates. Several improvements to that algorithm are described which make the approach applicable and computationally efficient for almost any geometry of conductors in a homogeneous dielectric. Results using these techniques in a program which computes the capacitance of general 3D structures are presented to demonstrate that the new algorithm is nearly as accurate as the more standard direct factorization approach, and is more than two orders of magnitude faster for large examples. (18 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B0290F (Interpolation and function approximation); B0290T (Finite element analysis); C7410D (Electronic engineering computing); C4130 (Interpolation and function approximation); C4185 (Finite element analysis) Thesaurus: Boundary-elements methods; Capacitance; Computational complexity; Electronic engineering computing; Iterative methods; Packaging Free Terms: Multiconductor structures; Fast capacitance extraction; IC packaging; Three-dimensional structures; Boundary-element-based algorithm; Computational complexity; Conjugate residual iterative technique; Multipole algorithm; Homogeneous dielectric Item Availability: CD-ROM. INSPEC 4224940 B9210-0170J-023 C9210-6130B-044 Doc Type: Conference Paper Title: 3-D solid modeling for assembly design Authors: DeRosa, J.; McGrath, J. Affiliation: Digital Equipment Corp., Hudson, MA, USA Conf. Title: IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.91CH3042-9) p. 128-30 Publisher: IEEE New York, NY, USA Date: 1991 x+212 pp. Country of Publication: USA ISBN: 0 7803 0152 8 CCC: CH3042-9/91/0000-0128$01.00 Language: English Conf. Date: 21-23 Oct. 1991 Conf. Loc: Boston, MA, USA Conf. Sponsor: IEEE; Semiconductor Equipment & Mater. Int Treatment: General/Review; Practical Abstract: The authors describe a solid model 3-D CAD (computer-aided design) tool that was used by a concurrent engineering integrated circuit assembly team. Parameter and tolerance designs were established in the design phase of the ceramic pin grid array package cavity. The results supported standard wire bond technology for 5 mil pitch chip pads and suggest the choice of an orthogonal pad design as the most robust package and layout. The ability to illustrate various conditions by changing process and piece part tolerances before tooling was the key to assuring a design for maximum manufacturability. (8 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B2570 (Semiconductor integrated circuits); B0170C (Project and design engineering); C6130B (Graphics techniques); C7410D (Electronic engineering computing) Thesaurus: CAD; Engineering graphics; Lead bonding; Packaging; Solid modelling; VLSI Free Terms: 3D CAD tool; Parameter design; Fine pitch chip pads; Robust layout; Design for manufacturability; 3-D solid modeling; Assembly design; Concurrent engineering; Integrated circuit assembly; Tolerance designs; Design phase; Ceramic pin grid array package cavity; Wire bond technology; Orthogonal pad design; Robust package; Tolerances; Design for maximum manufacturability; 5 Mil Numerical Index: Distance 1.3E-04 m Item Availability: CD-ROM. INSPEC 4188859 B9208-5240-005 Doc Type: Conference Paper Title: Practical design for controlled impedance Authors: Canright, R.E., Jr. Affiliation: Martin Marietta Electron. Orlando, FL, USA Conf. Title: 1991 Proceedings. 41st Electronic Components and Technology Conference (Cat. No.91CH2989-2) p. 370-7 Publisher: IEEE New York, NY, USA Date: 1991 xvi+901 pp. Country of Publication: USA ISBN: 0 7803 0012 2 CCC: 0569-5503/91/0000-0370$01.00 Language: English Conf. Date: 11-16 May 1991 Conf. Loc: Atlanta, GA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Theoretical/Mathematical Abstract: A novel method for designing controlled impedance transmission lines for high-speed digital systems is introduced. The method requires specification of the desired electrical performance, some device parameters, and the desired characteristic impedance (Z/sub 0/). By following this procedure, the minimum and maximum Z/sub 0/ values that meet electrical performance and the useful tolerances on the nominal Z/sub 0/ are maximized. The value of the termination resistor that maximizes the tolerances on Z/sub 0/ is also obtained. In the ideal case of transmission line termination, the termination resistor matches the line impedance. In the practical case, the optimum series termination resistor for high-speed digital systems is less than the nominal line impedance. The optimum parallel termination resistor will have a higher value than the nominal line impedance. (7 Refs.) Classification: B5240 (Transmission line theory); B0170J (Product packaging); B1265 (Digital electronics) Thesaurus: Digital circuits; Digital systems; Impedance matching; Packaging; Transmission line theory Free Terms: Design method; Controlled impedance transmission lines; High-speed digital systems; Characteristic impedance; Optimum series termination resistor; Optimum parallel termination resistor Item Availability: CD-ROM. INSPEC 4188856 B9208-2240-003 Doc Type: Conference Paper Title: Z-axis conductive adhesive for TAB and fine pitch interconnects Authors: Chung, K.; Dreier, G.; Fitzgerald, P.; Boyle, A.; Lin, M.; Sager, J. Affiliation: AI Technol. Inc., Princeton, NJ, USA Conf. Title: 1991 Proceedings. 41st Electronic Components and Technology Conference (Cat. No.91CH2989-2) p. 345-54 Publisher: IEEE New York, NY, USA Date: 1991 xvi+901 pp. Country of Publication: USA ISBN: 0 7803 0012 2 CCC: 0569-5503/91/0000-0345$01.00 Language: English Conf. Date: 11-16 May 1991 Conf. Loc: Atlanta, GA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Application; Practical Abstract: Solder are used extensively in both die-attach and component attach in the first and second levels of electronic packaging. With the commercialization of VLSI and ULSI devices, both levels of fabrication have encountered difficulties in both manufacturability and reliability. These problems are analyzed and a novel solution of Z-axis, 'stress-free', and thermally conductive adhesives are introduced. The adhesive system has been engineered to simulate all the desirable characteristics of soldering such as fast 'curing' speed (milliseconds), ambient storage, low thermal and low electrical contact resistances, and reworkability. The drawbacks of solders, such as fatigue failures, stress-induced failures, and bridging, are avoided. All of these basic properties and some of the applications are discussed. (20 Refs.) Classification: B2240 (Microassembly techniques); B0170J (Product packaging); B2210D (Printed circuit manufacture); B2220C (General integrated circuit fabrication techniques) Thesaurus: Adhesion; Integrated circuit manufacture; Packaging; Printed circuit manufacture; Surface mount technology; Tape automated bonding Free Terms: Stress-free adhesives; VLSI devices; Z-axis conductive adhesive; TAB; Fine pitch interconnects; Die-attach; Component attach; Electronic packaging; ULSI devices; Fabrication; Manufacturability; Thermally conductive adhesives Item Availability: CD-ROM. INSPEC 4128021 B9205-1130B-035 C9205-7410D-138 Doc Type: Conference Paper Title: Fast capacitance extraction of general three-dimensional structures Authors: Nabors, K.; Kim, S.; White, J.; Senturia, S. Affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA Conf. Title: IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3) p. 479-84 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xvi+654 pp. Country of Publication: USA ISBN: 0 8186 2270 9 CCC: CH3040-3/91/0000-0479$01.00 Language: English Conf. Date: 14-16 Oct. 1991 Conf. Loc: Cambridge, MA, USA Conf. Sponsor: IEEE Treatment: Practical; Theoretical/Mathematical Abstract: Several improvements to the multipole-accelerated 3-D capacitance extraction program previously described are presented. A new adaptive multipole algorithm is given, and a preconditioning strategy for accelerated iterative method convergence is described. Results using these algorithms to compute the capacitance of general three-dimensional structures are presented, and they demonstrate that the modified approach is nearly as accurate as the more standard direct factorization algorithm, and can be as much as two orders of magnitude faster. (6 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B0290F (Interpolation and function approximation); C7410D (Electronic engineering computing); C4130 (Interpolation and function approximation) Thesaurus: Capacitance; Circuit CAD; Convergence of numerical methods; Electronic engineering computing; Integrated circuit technology; Iterative methods; Packaging Free Terms: Three-dimensional structures; Multipole-accelerated 3-D capacitance extraction program; Adaptive multipole algorithm; Preconditioning strategy; Accelerated iterative method convergence; Direct factorization algorithm Item Availability: CD-ROM. INSPEC 4128019 B9205-2210B-010 Doc Type: Conference Paper Title: Fine-line printed circuit board for high-performance computer design Authors: Huang, C.-C.; Willis, J.; Schmitt, T. Affiliation: Compunetics Inc., Monroeville, PA, USA Conf. Title: IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3) p. 468-71 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xvi+654 pp. Country of Publication: USA ISBN: 0 8186 2270 9 CCC: CH3040-3/91/0000-0468$01.00 Language: English Conf. Date: 14-16 Oct. 1991 Conf. Loc: Cambridge, MA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: Properties of a new fine-line printed circuit board which are critical in the design of computer systems based on GaAs, 100 K and 10 K logic families, are characterized. The new PCB technology permits trace widths as fine as 0.002 in. on the inner layers of multilayer boards. While facilitating higher package density and controlled impedance interconnects with higher characteristic impedance (Z/sub 0/), the technology opens questions of thermal reliability, ohmic heating, and noise margin. Cross-validating analytic and laboratory analysis is used to investigate each of these issues. Provided that several key issues are addressed during design, this report supports the use of 0.002 in. technology in high-performance computer systems. (4 Refs.) Classification: B2210B (Printed circuit layout and design); B0170J (Product packaging) Thesaurus: Circuit layout; Packaging; Printed circuits Free Terms: Computer design; Fine-line printed circuit board; Logic families; PCB technology; Trace widths; Inner layers; Multilayer boards; Package density; Controlled impedance interconnects; Characteristic impedance; Thermal reliability; Ohmic heating; Noise margin Item Availability: CD-ROM. INSPEC 4111834 B9204-1265F-068 C9204-5130-039 Doc Type: Conference Paper Title: Superintegrated smart access controller Authors: Kumar, N.; Swami, R.; Nimishakavi, H.; Nobugaki, I.; Sen, A. Affiliation: Zilog Inc., Campbell, CA, USA Conf. Title: Proceedings. Third Annual IEEE ASIC Seminar and Exhibit (Cat. No.90TH0303-8) p. P2/5.1-4 Editors: Hsu, K.W.; Schrader, M.E. Publisher: IEEE New York, NY, USA Date: 1990 xviii+656 pp. Country of Publication: USA CCC: TH0303-8/90/0000-P2-5.1$01.00 Language: English Conf. Date: 17-21 Sept. 1990 Conf. Loc: Rochester, NY, USA Conf. Sponsor: IEEE Treatment: Practical; Product review; Experimental Abstract: The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package. (0 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570D (CMOS integrated circuits); B0170J (Product packaging); C5130 (Microprocessor chips) Thesaurus: Application specific integrated circuits; CMOS integrated circuits; Microcontrollers; Packaging; VLSI Free Terms: Zilog; Smart access controller; Serial communication control applications; Terminals; Printers; Modems; Slave communication processes; MPU-based systems; Cost reductions; Serial communication controller; Z80180 MPU; Features; Low electromagnetic interference; Programmable interrupt priority daisy chain; Megacell-based superintegration design methodology; CMOS technology; Die size; QFP; Package; 8 To 32 bit; 8 Bit; 1.2 Micron; 330 Mil; 205 Mil Numerical Index: Word length 8.0E+00 to 3.2E+01 bit; Word length 8.0E+00 bit; Size 1.2E-06 m; Size 8.4E-03 m; Size 5.21E-03 m Item Availability: CD-ROM. INSPEC 4092510 B9204-6230F-006 Doc Type: Journal Paper Title: Physical design issues for very large ATM switching systems Authors: Banwell, T.C.; Estes, R.C.; Habiby, S.F.; Hayward, G.A.; Helstern, T.K.; Lalk, G.R.; Mahoney, D.D.; Wilson, D.K.; Young, K.C., Jr Affiliation: Bellcore, Morristown, NJ, USA Journal: IEEE Journal on Selected Areas in Communications Vol: 9 Iss: 8 p. 1227-38 Date: Oct. 1991 Country of Publication: USA ISSN: 0733-8716 CODEN: ISACEM CCC: 0733-8716/91/1000-1227$01.00 Language: English Treatment: Practical Abstract: The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed. (26 Refs.) Classification: B6230F (Integrated switching and transmission systems); B6210M (ISDN); B6260 (Optical links and equipment); B0170J (Product packaging) Thesaurus: Broadband networks; Electronic switching systems; ISDN; Optical communication equipment; Optical links; Packaging; Time division multiplexing Free Terms: Speed requirements; Broadband networks; B-ISDN; Optical networks; Large ATM switching systems; Physical design issues; Terabit/second switching systems; Customer access portion; Backplane interconnections; Integrated circuit packaging; Circuit board technology; 3D interconnection architecture; Multichip module technology; Density requirements Item Availability: CD-ROM. INSPEC 4078833 B9203-0170J-024 Doc Type: Journal Paper Title: 3-D electromagnetic field analysis of interconnections in copper-polyimide multichip modules Authors: Sasaki, S.; Konno, R.; Tomimuro, H.; Ohsaki, T. Affiliation: NTT Corp., Tokyo, Japan Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 14 Iss: 4 p. 755-60 Date: Dec. 1991 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/91/1200-0755$01.00 Language: English Treatment: Theoretical/Mathematical Abstract: A three-dimensional electromagnetic field analysis of interconnections in copper-polyimide multichip modules is described. This analysis is based on the spatial network method: a lattice network model of Maxwell's equation formulated in the time domain by Bergeron's method. Results of simulating reflection and transmission waves at interconnections are presented. Frequency characteristics of the scattering parameter S/sub 21/ are calculated using the fast Fourier transform (FFT). The 3-dB down cutoff frequencies of wire bonded, tape automated bonding (TAB), and flip-chip bonding (FCB) interconnections are, respectively, 6, 14, and 40 GHz; those of interconnection vias are over 200 GHz. Copper-polyimide multichip modules can, therefore, be applied to ultra-high-speed systems. (17 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits); B5100 (Electric and magnetic fields) Thesaurus: Copper; Electromagnetic fields; Fast Fourier transforms; Flip-chip devices; Integrated circuit technology; Modules; Packaging; Polymer films; S-parameters; Tape automated bonding Free Terms: Time domain formulation; Reflection waves; Scattering parameter frequency characteristics; Wire bonding; Interconnections; Copper-polyimide multichip modules; Three-dimensional electromagnetic field analysis; Spatial network method; Lattice network model; Maxwell's equation; Bergeron's method; Transmission waves; Fast Fourier transform; Cutoff frequencies; TAB; Flip-chip bonding; Interconnection vias; Ultra-high-speed systems; 6 GHz; 14 GHz; 40 GHz; Cu Numerical Index: Frequency 6.0E+09 Hz; Frequency 1.4E+10 Hz; Frequency 4.0E+10 Hz Chemical Index: Cu/int Cu/el Item Availability: CD-ROM. INSPEC 4076729 B9203-2570-011 Doc Type: Conference Paper Title: An overview and analysis of 3D WSI Authors: McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9) p. 223-35 Editors: Little, M.J.; Jain, V.K. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9126 3 Language: English Conf. Date: 29-31 Jan. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: General/Review; Theoretical/Mathematical Abstract: The author reviews the early trends in 3-D WSI (wafer scale integration) and examines recent breakthroughs in technology to assess the viability of 3-D. It is concluded that this option is rich with possibility for the designer. However, not every architecture can benefit equally from this packaging approach. An attempt is made to quantify this impact by computing an average wire-shortening effect from 3-D partitioning, but even this average improvement is pessimistic if the given architecture is such that the most critical paths can all be placed on the vertical wiring runs in the stack, depending on the vertical spacing of the wafers. (13 Refs.) Classification: B2570 (Semiconductor integrated circuits); B1265F (Microprocessors and microcomputers); B0170J (Product packaging); B2220J (Hybrid integrated circuits) Thesaurus: Hybrid integrated circuits; Microprocessor chips; Packaging; VLSI Free Terms: WSI stacking; Overview; Analysis; 3D WSI; Wafer scale integration; Breakthroughs in technology; Viability of 3-D; Average wire-shortening effect; 3-D partitioning; Critical paths; Vertical wiring runs; Vertical spacing Item Availability: CD-ROM. INSPEC 4076726 B9203-2220J-009 Doc Type: Conference Paper Title: Comparing monolithic and hybrid WSI massively parallel processing modules for cost-effective real-time signal and data processing Authors: Lea, R.M. Affiliation: Aspex Microsyst., Brunel Univ., Uxbridge, UK Conf. Title: 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9) p. 199-206 Editors: Little, M.J.; Jain, V.K. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9126 3 Language: English Conf. Date: 29-31 Jan. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: General/Review; Experimental Abstract: It is demonstrated that wafer-scale-integration associative string processor (WSI ASP) module components offer a 150-800 times improvement in TOPS (tera operations per second)/ft/sup 3/, a 13 times improvement in GOPS (giga operations per second)/W and a 14-44 times improvement in MOPS (mega operations per second)/$ over VLSI components. For all three figures-of-merit monolithic-WSI ASP modules have an advantage over hybrid WSI ASP modules. In addition, the inherent defect-tolerance in the manufacture of monolithic-WSI ASP modules offers fault-tolerance in service, which the hybrid-WSI ASP could only match with an increase in chip size and cost. Lastly, and significantly for the future, the precisely regular layout of monolithic-WSI ASP wafers renders them excellent candidates for highly-compact 3-D packaging techniques, offering significant improvements in TOPS/ft/sup 3/ which could not be achieved with hybrid-WSI. (4 Refs.) Classification: B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits); B1265F (Microprocessors and microcomputers); B0170J (Product packaging) Thesaurus: Hybrid integrated circuits; Microprocessor chips; Multiprocessing systems; Packaging; VLSI Free Terms: Cost effective signal processing; TOPS/ft/sup 3/ improvement; GOPS/W improvement; MOPS/Dollar improvement; WASP; WSI massively parallel processing modules; Wafer-scale-integration associative string processor; Figures-of-merit; Hybrid WSI ASP modules; Defect-tolerance; Monolithic-WSI ASP modules; Fault-tolerance in service; Regular layout; 3-D packaging techniques Item Availability: CD-ROM. INSPEC 4067345 B9202-2220J-030 Doc Type: Conference Paper Title: Layout design of VLSI multichip packaging Authors: Zhou, D. Affiliation: Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA Conf. Title: IEEE Proceedings of SOUTHEASTCON '91 (Cat. No.91CH2998-3) p. 129-32 vol.1 Publisher: IEEE New York, NY, USA Date: 1991 2 vol. 1256 pp. Country of Publication: USA ISBN: 0 7803 0033 5 CCC: CH2998-3/91/0000-0129$01.00 Language: English Conf. Date: 7-10 April 1991 Conf. Loc: Williamsburg, VA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: The nature of multichip module layout is explored, and several associated fundamental design problems are discussed. In particular, problems of decomposing a three-dimensional layout into a set of single-layer layouts and techniques of incorporating performance requirements into a single-layer layout are studied. (16 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B2220E (Thin film circuits); B1110 (Network topology) Thesaurus: Circuit layout; Hybrid integrated circuits; Integrated circuit technology; Modules; Packaging; Thin film circuits; VLSI Free Terms: 3D layout decomposition; MCM technology; Topological routeing; VLSI multichip packaging; Multichip module layout; Three-dimensional layout; Single-layer layouts; Performance requirements Item Availability: CD-ROM. INSPEC 4067323 B9202-0170J-054 Doc Type: Conference Paper Title: The 3D interconnection-an enhanced densification approach with bare chips Authors: Val, C. Affiliation: Thomson-CSF, Colombes, France Conf. Title: 8th IEMT 1990. International Electronic Manufacturing Technology Symposium (Cat. No.90CH2833-2) p. 82-91 Publisher: IEEE New York, NY, USA Date: 1990 viii+515 pp. Country of Publication: USA CCC: CH2833-2/90/0000-0082$01.00 Language: English Conf. Date: 7-9 May 1990 Conf. Loc: Baveno, Italy Conf. Sponsor: IEEE Treatment: Practical Abstract: The author proposes interconnecting the bare chips along the Z axis rather than in the XY plane, thereby enabling a large enhancement of densification (by a factor of five to eight). This technique also substantially improves the high-frequency behavior of ICs. Inductances are very low, for example, since the longest conductor will not exceed 4.8 mm in length. In addition, the capacitances of the conductors, compared with those of the chips' silicon lateral areas, are 10 to 100 times less than they would be with an on-polyimide thin-film interconnection. An application consisting of a cube of eight stacked 256-kb SRAMs is presented. (6 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Integrated circuit technology; Modules; Packaging Free Terms: Inductance; Conductor capacitance; Multichip module; Stacked SRAMs; Cube packaging; 3D interconnection; Enhanced densification; Bare chips; High-frequency behavior Item Availability: CD-ROM. INSPEC 4038332 B9201-2570D-019 C9201-5440-020 Doc Type: Conference Paper Title: A 3-D wafer scale architecture for early vision processing Authors: Toborg, S.T. Affiliation: Hughes Res. Lab., Malibu, CA, USA Conf. Title: Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7) p. 247-58 Editors: Sun-Yuan Kung; Swartzlander, E.E.; Fortes, J.A.B.; Przytula, K.W. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1990 xii+808 pp. Country of Publication: USA ISBN: 0 8186 9089 5 CCC: CH2920-7/90/0000/0247$01.00 Language: English Conf. Date: 5-7 Sept. 1990 Conf. Loc: Princeton, NJ, USA Conf. Sponsor: IEEE; Ind. Dev. Board for Northern Ireland; NEC Res. Inst Treatment: General/Review; New development; Practical Abstract: A massively parallel SIMD cellular computer is designed for processing early vision algorithms based on regularization theory and Markov random field (MRF) models. Algorithmic requirements and implementation issues are reviewed in detail for edge detection/surface reconstruction. The development of 3-D wafer scale integration (WSI) technologies that offer an ideal medium for implementing many early vision algorithms is discussed. An edge detection algorithm is mapped to the 3-D WSI computer that consists of a 128*128 array of processors formed by stacking 15 four inch CMOS wafers. This mapping is used as the basis for an enhanced array processor tailored for multiresolution MRF processing. Enhancements are proposed that would boost peak performance to over a trillion operations per second, using a stack of 40 wafers, with a total system volume of 820 cm/sup 3/ and consuming about 370 W. (15 Refs.) Classification: B2570D (CMOS integrated circuits); B0170J (Product packaging); C5440 (Multiprocessing systems); C5260B (Computer vision and image processing techniques); C5220P (Parallel architecture) Thesaurus: CMOS integrated circuits; Computerised picture processing; Packaging; Parallel architectures; Parallel machines; Systolic arrays; VLSI Free Terms: Wafer stacking; Surface reconstruction; Four inch wafers; Markov random field models; 3-D wafer scale architecture; Early vision processing; Massively parallel SIMD cellular computer; Regularization theory; Edge detection algorithm; 3-D WSI computer; Array of processors; CMOS; Enhanced array processor; Multiresolution MRF processing; System volume; 4 In; 370 W Numerical Index: Size 1.0E-01 m; Power 3.7E+02 W Item Availability: CD-ROM. INSPEC 4000134 B91067558 Doc Type: Conference Paper Title: Effect of case temperature measurement errors on the junction-to-case thermal resistance of a ceramic PGA Authors: Kozarek, R.L. Affiliation: Aluminum Co. of America, Alcoa Center, PA, USA Conf. Title: 1991 Proceedings, Seventh Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.91CH2972-8) p. 44-51 Publisher: IEEE New York, NY, USA Date: 1991 ix+176 pp. Country of Publication: USA ISBN: 0 87942 664 0 CCC: CH2972-8/91/0000-0044$01.00 Language: English Conf. Date: 12-14 Feb. 1991 Conf. Loc: Phoenix, AZ, USA Conf. Sponsor: IEEE; NIST Treatment: Theoretical/Mathematical; Experimental Abstract: The author describes an experimental investigation in which measurements of junction-to-case thermal resistance, theta /sub jc/, of a 132-pin cavity-down ceramic (PGA) pin grid array package are compared to finite element (FEM) calculations. The initial goal of this work was to validate FEM predictions of theta /sub jc/ with measurements in accordance with the established SEMI and MIL standards. A serious problem was discovered in measuring accurate case temperatures, resulting in poor agreement between measured and predicted theta /sub jc/. Detailed 3-D FEM simulations were used to analyze thermocouple measurement problems in the region between the case and cold plate. New methods were developed using fiber-optic thermometry and surface-junction thermocouples. (7 Refs.) Classification: B0170J (Product packaging); B7320R (Thermal variables measurement); B7230 (Sensing devices and transducers) Thesaurus: Fibre optic sensors; Finite element analysis; Measurement errors; Packaging; Spectral methods of temperature measurement; Temperature measurement; Thermal resistance; Thermocouples Free Terms: Thermal simulation; Case temperature measurement errors; Junction-to-case thermal resistance; Ceramic PGA; Pin grid array package; FEM; Thermocouple measurement problems; Fiber-optic thermometry; Surface-junction thermocouples Item Availability: CD-ROM. INSPEC 3971281 B91062421 Doc Type: Journal Paper Title: Circuitry in three dimensions: multifunctional molded plastic packages Authors: Frisch, D.C. Affiliation: Mitsui-Pathtek Corp., Rochester, NY, USA Journal: IEEE Transactions on Industry Applications Vol: 27 Iss: 3 p. 442-6 Date: May-June 1991 Country of Publication: USA ISSN: 0093-9994 CODEN: ITIACR CCC: 0093-9994/91/0500-0442$01.00 Language: English Treatment: Practical Abstract: The topics dealt with are: some of the major structural/mechanical benefits of a molded circuit board; some of the material benefits of a molded circuit board; high-heat thermoplastics; resin materials for molded circuit interconnect fabrication; MCB metallization; MCB general properties; molded circuit interconnect applications; and the future of performance plastics and 3D molded circuit interconnects. Molded circuits consolidate circuitry, wiring and hardware into a one piece construction. The resultant integral assembly provides increased reliability and reduced costs. Elements of cost savings include reduced factory labor, parts consolidations, simplified product assembly, lighter weight, compact size, and unique function. (5 Refs.) Classification: B2210 (Printed circuits); B0170J (Product packaging); B0560 (Polymers and plastics (engineering materials science)) Thesaurus: Packaging; Plastics; Polymers; Printed circuits; Wiring Free Terms: Packages; Molded circuit board; Material; Thermoplastics; Resin; Circuit interconnect fabrication; Metallization; Performance; 3D; Wiring; Integral assembly; Reliability; Costs Item Availability: CD-ROM. INSPEC 3971186 A91114005 B91063376 Doc Type: Journal Paper Title: Frequency domain optical network analysis using integrated optics Authors: Jungerman, R.L.; Dolfi, D.W. Affiliation: Hewlett Packard Co., Santa Rosa, CA, USA Journal: IEEE Journal of Quantum Electronics Vol: 27 Iss: 3 p. 580-7 Date: March 1991 Country of Publication: USA ISSN: 0018-9197 CODEN: IEJQA7 CCC: 0018-9197/91/0300-0580$01.00 Language: English Treatment: Application; Experimental Abstract: Frequency domain based measurements of optical networks and components are reviewed. A measurement system for performing optical network analysis is described in detail. The application of a Ti:LiNbO/sub 3/ Mach-Zehnder modulator in such a network analyzer is discussed. The integrated optic modulator makes it possible to characterize both the amplitude and phase of the modulation response of lightwave components. The modulator operates at both 1300 and 1550 nm. Design considerations and tradeoffs are described to obtain the wide wavelength coverage, as well as low switching voltage and a stable frequency response which can be calibrated. Device pigtailing, packaging, and reliability are discussed as they relate to overall instrument reliability. Stability considerations including bias drift and acoustic resonances are detailed for both x- and z-cut modulators. (34 Refs.) Classification: A0760H (Optical refractometry and reflectometry); A4280K (Optical beam modulators); A4282 (Integrated optics); B4140 (Integrated optics) Thesaurus: Amplitude modulation; Frequency-domain analysis; Integrated optics; Optical modulation; Phase modulation; Reflectometry Free Terms: Amplitude modulation; Phase modulation; X-cut modulators; Calibration; Optical frequency domain reflectometry; Optical network analysis; Integrated optics; Measurement system; Mach-Zehnder modulator; Network analyzer; Integrated optic modulator; Modulation response; Lightwave components; Wide wavelength coverage; Low switching voltage; Stable frequency response; Pigtailing; Packaging; Reliability; Bias drift; Acoustic resonances; Z-cut modulators; 1300 Nm; 1550 Nm; LiNbO/sub 3/:Ti Numerical Index: Wavelength 1.3E-06 m; Wavelength 1.55E-06 m Chemical Index: LiNbO3:Ti/ss LiNbO3/ss NbO3/ss Li/ss Nb/ss O3/ss Ti/ss O/ss Ti/el Ti/dop Item Availability: CD-ROM. INSPEC 3966304 A91116132 Doc Type: Conference Paper Title: 3-D field and particle simulations with ARGUS Authors: Mankofsky, A.; Chang, C.L.; Drobot, A.; Grossmann, W.; Kress, M.; Mondelli, A.; Petillo, J.; Brandon, S.; Ko, K. Affiliation: Sci. Applications Int. Corp., McLean, VA, USA Conf. Title: Conference Record - Abstracts. 1990 IEEE International Conference on Plasma Science (Cat. No.90CH2857-1) p. 102 Publisher: IEEE New York, NY, USA Date: 1990 231 pp. Country of Publication: USA Language: English Conf. Date: 21-23 May 1990 Conf. Loc: Oakland, CA, USA Conf. Sponsor: IEEE Treatment: Theoretical/Mathematical Abstract: Summary form only given. The ARGUS three-dimensional simulation code has been used for a wide variety of problems which require the solution of field equations and particle flows in complex geometries. Some of the applications include the determination of resonant modes in RF and accelerator structures, the electrical stability of MMIC (microwave monolithic integrated circuit) packaging, antenna design, gun design. the calculation of S-parameters for solid-state devices, and the calculation of RF component characteristics in the presence of dielectrics and magnetic materials. Combinatorial geometry is used in ARGUS to configure simulations for a wide class of problems. In applying ARGUS to the large problem set described above, it has been possible to verify the ability of large E-M simulation codes to produce accurate solutions, and to do so in a way that is useful for design. (0 Refs.) Classification: A5265 (Plasma simulation) Thesaurus: Plasma simulation Free Terms: Combinatorial geometry; Particle simulations; ARGUS three-dimensional simulation code; Field equations; Particle flows; Complex geometries; Resonant modes; Accelerator structures; Electrical stability; MMIC; Microwave monolithic integrated circuit; Packaging; Antenna design; Gun design; S-parameters; Solid-state devices; RF component characteristics; Dielectrics; Magnetic materials Item Availability: CD-ROM. INSPEC 3956560 B91054511 Doc Type: Conference Paper Title: A precision vertical interconnect technology Authors: Greenstein, M.; Matta, F. Affiliation: Hewlett-Packard Lab., Palo Alto, CA, USA Conf. Title: Ninth IEEE/CHMT International Electronic Manufacturing Technology Symposium. Competitive Manufacturing for the Next Decade. Proceedings 1990 IEMT Symposium (Cat. No. 89CH2864-7) p. 208-15 Publisher: IEEE New York, NY, USA Date: 1990 x+370 pp. Country of Publication: USA CCC: CH2864-7/90/0000-0208$01.00 Language: English Conf. Date: 1-3 Oct. 1990 Conf. Loc: Washington, DC, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: An interconnection technology is described that utilizes excimer laser drilled vias and computer controlled plating to provide vertical (Z-axis) electrical connections in high-performance flexible circuits. Specifically, solid vias and hemispherical microcontacts are created with a 1- mu m nearest-neighbor height precision for the microcontacts. An architecture with a novel structure is employed to simplify the ground plane connections for impedance controlled flex circuits. The rationale for material and unit-process selection is described. The laser drilling of holes for the vertical interconnects is outlined. The deposition of the metal interconnects is considered. The performance of the resulting structures is characterized. This technology was implemented with a polyimide substrate and nickel contacts. (6 Refs.) Classification: B0170J (Product packaging); B4360 (Laser applications); B2180 (Electrical contacts) Thesaurus: Electrical contacts; Electroplating; Laser beam machining; Nickel; Packaging Free Terms: Vertical interconnect technology; Excimer laser drilled vias; Computer controlled plating; High-performance flexible circuits; Solid vias; Hemispherical microcontacts; Nearest-neighbor height precision; Ground plane connections; Impedance controlled flex circuits; Unit-process selection; Metal interconnects; Polyimide substrate; Ni contacts Chemical Index: Ni/int Ni/el Item Availability: CD-ROM. INSPEC 3897491 B91037029 Doc Type: Conference Paper Title: Signal integrity analysis of high-speed, high-pin-count digital packages Authors: Tsai, C.-T. Affiliation: Motorola Semicond. Products Sect., Chandler, AZ, USA Conf. Title: 1990 Proceedings. 40th Electronic Components and Technology Conference (Cat. No.90CH2893-6) p. 1098-107 vol.2 Publisher: IEEE New York, NY, USA Date: 1990 2 vol. xvi+1125 pp. Country of Publication: USA CCC: 0569-5503/90/0000-1098$01.00 Language: English Conf. Date: 20-23 May 1990 Conf. Loc: Las Vegas, NV, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical; Experimental Abstract: A transmission-line model of package traces in conjunction with a lattice diagram technique is used to study the signal integrity problem in digital systems using high-speed, high-pin-count packages. Formulae which predict the signal degradations, including overshoot/undershoot and edge-rate degradation, are presented for two different high-speed digital system interconnect schemes (parallel termination and series termination) at different locations of the interconnect (output, input, package-board junction, etc.) Among different degradations at various places on the interconnect, the one of most concern to system designers is the reflection noise in multiple fanouts or bidirectional buffers. An experimental procedure was developed to verify this problem and to quantitatively measure the magnitude of the reflection noise. An experimental 288-PGA (pin-grid-array) package which may represent the current package technology was chosen for this experiment. The results clearly indicate that package parasitics can substantially affect the signal integrity of current high-speed digital systems. According to the present study, it is not possible to choose a single package impedance Z/sub p/ which can give optimized signal response everywhere along the interconnect. It may be a design tradeoff to choose a particular package impedance for a specific system. However, the study also indicates that choosing a package impedance is far less important that minimizing the package delay. (6 Refs.) Classification: B0170J (Product packaging) Thesaurus: Delays; Digital systems; Packaging Free Terms: High-pin-count digital packages; Transmission-line model; Package traces; Lattice diagram technique; Digital systems; Signal degradations; Overshoot/undershoot; Edge-rate degradation; Parallel termination; Series termination; Package-board junction; Reflection noise; Multiple fanouts; Bidirectional buffers; Pin-grid-array; Package parasitics; Optimized signal response; Package delay Item Availability: CD-ROM. INSPEC 3897413 B91037007 Doc Type: Conference Paper Title: 3D interconnection for ultra-dense multichip modules Authors: Val, C.; Lemoine, T. Affiliation: Thomson-CSF, Colombes, France Conf. Title: 1990 Proceedings. 40th Electronic Components and Technology Conference (Cat. No.90CH2893-6) p. 540-7 vol.1 Publisher: IEEE New York, NY, USA Date: 1990 2 vol. xvi+1125 pp. Country of Publication: USA CCC: 0569-5503/90/0000-0540$01.00 Language: English Conf. Date: 20-23 May 1990 Conf. Loc: Las Vegas, NV, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: The increasing density of the interconnection of ASICs (application-specific integrated circuits) and memories is discussed. It is demonstrated that the interconnections of ASICs require the utilization of thin-film multilayers. However, since ASICs are interconnected in an extremely dense manner, the relative area occupied by the memories increases substantially, and currently amounts to approximately 50%. The 3-D interconnection technology allows reduction of the occupied area by a factor of 7 or 8 and thus yielded ultradense multichip modules. This interconnection approach consists of interconnecting the bare chips not in the xy plane but along the z axis. The interconnection process entails interconnecting the four sides of the cube formed by stacking n chips (n=8 by 10) on top of one another. To do so, the chips are individually interconnected on a thin film identical to a TAB (tape automated bonding) film by means of gold wires prior to cubing. This technique also substantially improves the high-frequency behavior of ICs. An application consisting of a cube of eight stacked 256-kb static random-access memories is being developed. (11 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B1265D (Memory circuits) Thesaurus: Application specific integrated circuits; Modules; Packaging; SRAM chips; Tape automated bonding Free Terms: 3D interconnection; Ultra-dense multichip modules; ASICs; Thin-film multilayers; Memories; Bare chips; Interconnection process; Stacking; TAB; Cubing; High-frequency behavior; Static random-access memories Item Availability: CD-ROM. INSPEC 3875405 B91029556 Doc Type: Conference Paper Title: On the accommodation of coolant flow paths in high-density packaging Authors: Nakayama, W. Affiliation: Hitachi Ltd., Ibaraki, Japan Conf. Title: InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM II (Cat. No.90CH2798-7) p. 101-12 Publisher: IEEE New York, NY, USA Date: 1990 xii+180 pp. Country of Publication: USA CCC: CH2798-7/90/0000-0101$01.00 Language: English Conf. Date: 23-25 May 1990 Conf. Loc: Las Vegas, NV, USA Conf. Sponsor: IEEE; ASME; NIST; ISHM Treatment: Theoretical/Mathematical; Experimental Abstract: An analytical study was carried out to highlight the need to work out a tradeoff between the switching speed of logic gates and the average wiring distance, taking into account coolant flow distribution within the information processing system, in order to achieve the maximum processing speed at the system level. One of the models is composed of a row of gate-carrying cards flanked by side boards with networks to complete the three-dimensional wiring. The gates are cooled by forced convection of FC-77 or water. It is shown that the advantage of the 3D configuration in the reduction of wiring distance is seriously compromised by the need to make room for coolant channels within the system to such an extent that in certain cases the single-card system is favored over multiple-card systems. As a model of the single-card system, a square array of logic gates cooled by impinging liquid jets is considered. Again, it is concluded that the space requirement of coolant flows could set the upper bound for the density of logic gate packing. The case studies indicate that a gate-level heat flux of 100 W/cm/sup 2/ is a difficult target to achieve on a processor composed of a large number of gates. (16 Refs.) Classification: B0170J (Product packaging); B0170C (Project and design engineering) Thesaurus: Cooling; Design engineering; Digital circuits; Packaging Free Terms: Switching speed wiring distance tradeoff; Upper bound of logic gate density; FC-77 coolant; Water coolant; Accommodation of coolant flow paths; High-density packaging; Analytical study; Switching speed of logic gates; Average wiring distance; Coolant flow distribution; Information processing system; Row of gate-carrying cards; Boards with networks; Three-dimensional wiring; Forced convection; 3D configuration; Reduction of wiring distance; Room for coolant channels; Single-card system; Multiple-card systems; Square array of logic gates; Cooled by impinging liquid jets; Space requirement of coolant flows; Gate-level heat flux Item Availability: CD-ROM. INSPEC 3848405 B91022892 Doc Type: Journal Paper Title: Coupled noise and its effects on modern packaging technology Authors: Russ, S.H.; Alford, C.O. Affiliation: Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 13 Iss: 4 p. 1074-82 Date: Dec. 1990 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/90/1200-1074$01.00 Language: English Treatment: General/Review; Practical Abstract: An overview is presented of the causes of coupled noise and ways that coupled noise affects modern packaging technology. Two major types of coupled noise, crosstalk and switching noise, are discussed, with emphasis on physical causes and means of reducing both types. Major types of multiple-die hybrid and conventional packaging are described, and a case is made for the need for three-dimensional packaging. An example is presented of a low-noise packaging concept for 3-D integration. (24 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits) Thesaurus: Crosstalk; Integrated circuit technology; Noise; Packaging; Reviews Free Terms: Multiple-die hybrid packaging; 3D packaging; 3D integration; Packaging technology; Overview; Coupled noise; Crosstalk; Switching noise Item Availability: CD-ROM. INSPEC 3848395 B91022887 C91025044 Doc Type: Journal Paper Title: Substrate impact on the thermal performance of tape automated bonding components Authors: Davis, T.L. Affiliation: IBM Corp., Austin, TX, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 13 Iss: 4 p. 998-1005 Date: Dec. 1990 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/90/1200-0998$01.00 Language: English Treatment: Theoretical/Mathematical; Experimental Abstract: The results of thermally characterizing a 160-I/O (input/output) tape automated bonding (TAB) device are reported. A finite-element technique is used to understand and model the thermal processes of the TAB. A three-dimensional (3-D) computer model is developed and validated against experimental data obtained in a natural convection environment. The 3-D model's results indicate that the thermal processes associated with the TAB are not 2-D in nature. A substantial temperature variation is present across much of the device. Several carriers are modeled with the TAB device to determine their thermal effect on the device's thermal characteristics. Reducing the card's cross-section from a multilayer printed circuit board (PCB) to a board with no internal planes substantially impacts the power dissipation capabilities of the component. The use of a molded rather than an FR4 material in the card has a negligible effect on the thermal characteristics of the attached device due to their similar thermal conductivity. (6 Refs.) Classification: B0170J (Product packaging); B2210B (Printed circuit layout and design); B0290Z (Other numerical methods); B7320R (Thermal variables measurement); C7410D (Electronic engineering computing); C4190 (Other numerical methods) Thesaurus: Circuit analysis computing; Finite element analysis; Printed circuit design; Printed circuit testing; Substrates; Tape automated bonding; Thermal variables measurement Free Terms: Molded material; Packaging; Finite element model; Thermal performance; Tape automated bonding components; TAB; 3-D; Computer model; Natural convection; Temperature variation; Multilayer printed circuit board; PCB; Power dissipation; Thermal conductivity Item Availability: CD-ROM. INSPEC 3848372 B91024029 Doc Type: Journal Paper Title: 3-D interconnection for ultra-dense multichip modules Authors: Val, C.; Lemoine, T. Affiliation: Thomson-CSF, Colombes, France Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 13 Iss: 4 p. 814-21 Date: Dec. 1990 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/90/1200-0814$01.00 Language: English Treatment: New development; Practical; Experimental Abstract: A three-dimensional interconnection technology is described that allows a reduction of the occupied area by a factor of 7 or 8 as against 2-D interconnection. The approach consists of interconnecting the bare chips not in the XY plane, but along the Z-axis. The process entails interconnecting the four lateral areas (sides) of the cube formed by stacking n chips (n=8-10) on top of one another. The chips are individually interconnected on a thin film identical to a TAB (tape automatic bonded) film by means of gold wires, prior to cubing. These chips are standard, off-the-shelf, bump-free devices. After passing electrical testing and burn-in, they are then glued on top of one another with the TAB film. After these n chip+film assemblies have been cured (polymerized), a trim operation is carried out to cut the n-chips cube out of the TAB-film carrier cube. The trim line is approximately 100 mu m from the edge of the chips. The cube containing the n chips thus provides four lateral areas (sides) in which appear the cross sections of the gold wires connecting each lead of each chip to the corresponding leads on the flexible films. These gold wire cross-sections may be interconnected in two different ways according to the number of chip layouts/outputs or the conductor pitch. (10 Refs.) Classification: B2220J (Hybrid integrated circuits); B2240 (Microassembly techniques); B0170J (Product packaging) Thesaurus: Hybrid integrated circuits; Lead bonding; Modules; Packaging Free Terms: MCM; Of-the-shelf chips; Stacking bare chips; Vertical interconnection; Cube packaging; 3-D interconnection; Ultra-dense multichip modules; Three-dimensional interconnection technology; Z-axis; Bump-free devices; Glued on top of one another; TAB film; Trim operation; Au wire lead bonding Chemical Index: Au/el Item Availability: CD-ROM. INSPEC 3730998 B90059791 C90066279 Doc Type: Conference Paper Title: Electronic package thermal design using boundary elements Authors: Liu, J.C.; Hunter, D.E.; Kozerek, R.L. Affiliation: Aluminium Corp. of America, Alcoa Center, PA, USA Conf. Title: Sixth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium. SEMI-THERM Proceedings 1990 (Cat. No.90CH2640-1) p. 65-9 Publisher: IEEE New York, NY, USA Date: 1990 xiv+146 pp. Country of Publication: USA CCC: CH2640-1/90/0000-0065$1.00 Language: English Conf. Date: 6-8 Feb. 1990 Conf. Loc: Phoenix, AZ, USA Conf. Sponsor: IEEE Treatment: Application; Theoretical/Mathematical; Experimental Abstract: The use of the boundary-element method (BEM) for thermal evaluation of electronic packaging systems is discussed. Over the last twenty years, computer-aided engineering analysts have relied heavily on the finite-element method (FEM) for solving a variety of problems. This includes 2-D and 3-D linear or nonlinear heat transfer models on IC packages. However, the BEM, which discretizes only the problem boundary, provides a potentially faster method of modeling a problem. For 3-D models, in particular, parametric variations on a particular design can be evaluated more rapidly. This decreasing turnaround time will become a priority in future analyses of more sophisticated VLSI (very large scale integration) or PGA (pin grid array) packages which require design optimization on size and space arrangement for higher power capacity. BEM thermal models of 2-D and 3-D PGA packages were studied using the computer code BEASY. BEM results were compared to those of FEM models. A 3-D benchmark problem with documented experimental data was modeled to verify the BEM results. (10 Refs.) Classification: B0290F (Interpolation and function approximation); B0170J (Product packaging); B2570 (Semiconductor integrated circuits); C7410D (Electronic engineering computing) Thesaurus: Boundary-elements methods; CAD; Packaging; VLSI Free Terms: Models; Package thermal design; Boundary-element method; Thermal evaluation; Electronic packaging systems; Computer-aided engineering; Finite-element method; IC packages; 3-D models; Parametric variations; Turnaround time; VLSI; Very large scale integration; Pin grid array; Design optimization; Higher power capacity; BEM thermal models; PGA packages; Computer code BEASY; 3-D benchmark problem; Experimental data Item Availability: CD-ROM. INSPEC 3730997 B90059595 C90066278 Doc Type: Conference Paper Title: Carrier impact on the thermal performance of tape-automated-bonding components Authors: Davis, T.L. Affiliation: IBM Corp., Austin, TX, USA Conf. Title: Sixth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium. SEMI-THERM Proceedings 1990 (Cat. No.90CH2640-1) p. 58-64 Publisher: IEEE New York, NY, USA Date: 1990 xiv+146 pp. Country of Publication: USA CCC: CH2640-1/90/0000-0058$1.00 Language: English Conf. Date: 6-8 Feb. 1990 Conf. Loc: Phoenix, AZ, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: The results of thermally characterizing a 160 I/O tape-automated-bonding (TAB) component are discussed. A finite-element technique was employed to understand and model the thermal processes of the TAB. A three-dimensional computer model is developed and validated against experimental data obtained for a 160 I/O TAB in a natural convection environment. The results of the model indicate that the thermal processes associated with the TAB are not two dimensional in nature. A substantial temperature variation is present across much of the device. Several carriers are modeled with the TAB to determine their thermal effect on the device's thermal characteristics. Reducing the card's cross-section from a 2S2P to a no-internal-plane (NIP) construction substantially affects the power dissipation capabilities of the component. However, the use of a molded rather than a FR4 material in the card has a negligible effect on the thermal characteristics of the attached device due to their similar thermal conductivity. (6 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B1130B (Computer-aided circuit analysis and design); B0290F (Interpolation and function approximation); C7410D (Electronic engineering computing) Thesaurus: Cooling; Digital simulation; Finite element analysis; Lead bonding; Packaging Free Terms: Carrier impact; 160 Leaded component; 3D computer model; 2S2P cards; NIP cards; Thermal performance; Tape-automated-bonding components; Finite-element technique; Experimental data; Natural convection environment; Power dissipation capabilities; FR4 material Item Availability: CD-ROM. INSPEC 3719705 B90059594 Doc Type: Conference Paper Title: Thermal characteristics of single and multi-layer high performance PQFP packages Authors: Aghazadeh, M.; Mallik, D. Affiliation: Intel Corp., Chandler, AZ, USA Conf. Title: Sixth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium. SEMI-THERM Proceedings 1990 (Cat. No.90CH2640-1) p. 33-9 Publisher: IEEE New York, NY, USA Date: 1990 xiv+146 pp. Country of Publication: USA CCC: CH2640-1/90/0000-0033$1.00 Language: English Conf. Date: 6-8 Feb. 1990 Conf. Loc: Phoenix, AZ, USA Conf. Sponsor: IEEE Treatment: Practical; Theoretical/Mathematical; Experimental Abstract: Using experimental and computational techniques, it is shown that significant reduction in the package thermal resistance can be achieved by using a multilayer lead frame structure for medium and high lead count plastic quad flat pack (PQFP) packages. The thermal resistance of the 132 lead PQFP is reduced by 38% and 43% with copper and alloy 42 lead frames, respectively, under natural convection. A three-dimensional finite-element thermal model is constructed and correlated with the experimental data. Using this model, it is demonstrated that the contribution of the low thermal conductivity insulating adhesive tape to the overall thermal resistance is about 1 ( degrees C/W). In addition, increasing the power and ground plane thicknesses from 6 to 10 mils results in only about 1.5 ( degrees C/W) improvement in the junction-to-ambient thermal resistance. The thermal model is used to compare the thermal characteristics of the single-layer and multilayer PQFPs with copper and alloy 42 lead frames in the multicomponent board environment. The comparison indicates that the thermal resistance of the multilayer/alloy 42 lead frame PQFPs approach the thermal resistance of the multilayer/copper lead frame packages as the board temperature rises above the ambient temperature as a result of board heating. These packages will have similar thermal performance if the board temperature rises about 70 ( degrees C) above the ambient. (8 Refs.) Classification: B0170J (Product packaging) Thesaurus: Copper; Packaging; Thermal resistance Free Terms: High lead count PQFP; Plastic QFP; Thermal resistance reduction; 3D finite element thermal model; Single-layer PQFP; PQFP packages; Computational techniques; Package thermal resistance; Multilayer lead frame structure; Plastic quad flat pack; Alloy 42 lead frames; Natural convection; Low thermal conductivity insulating adhesive tape; Ground plane thicknesses; Junction-to-ambient thermal resistance; Thermal model; Multilayer PQFPs; Multicomponent board environment; Cu lead frame Chemical Index: Cu/el Item Availability: CD-ROM. INSPEC 3629251 B90035801 Doc Type: Journal Paper Title: The equivalent circuit of a microstrip crossover in a dielectric substrate Authors: Papatheodorou, S.; Harrington, R.F.; Mautz, J.R. Affiliation: Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA Journal: IEEE Transactions on Microwave Theory and Techniques Vol: 38 Iss: 2 p. 135-40 Date: Feb. 1990 Country of Publication: USA ISSN: 0018-9480 CODEN: IETMAB CCC: 0018-9480/90/0200-0135$01.00 Language: English Treatment: Theoretical/Mathematical Abstract: A quasi-static analysis is carried out to examine the capacitive coupling between two nonintersecting orthogonal microstrip lines above a ground plane and in a dielectric substrate. The charge density along the width of each strip is described using a prescribed charge distribution. A pair of coupled integral equations is derived and solved by the method of moments to obtain the excess charge densities. The lumped excess capacitances are computed and compared to those obtained using wire lines with radii equal to the equivalent radii of the strips. (17 Refs.) Classification: B1320 (Waveguide components); B1310 (Waveguides); B1350F (Solid-state microwave circuits and devices); B1190 (Other and miscellaneous topics in circuit theory); B0290R (Integral equations); B5240D (Waveguide and cavity theory) Thesaurus: Capacitance; Equivalent circuits; Green's function methods; Integral equations; Microwave integrated circuits; Strip line components; Strip lines; Waveguide theory Free Terms: Moments method; Electrostatic 3D Green's function; MIC; Microwave IC; Microwave packaging; Equivalent circuit; Microstrip crossover; Dielectric substrate; Quasi-static analysis; Capacitive coupling; Nonintersecting orthogonal microstrip lines; Ground plane; Charge density; Prescribed charge distribution; Coupled integral equations; Method of moments; Lumped excess capacitances Item Availability: CD-ROM. INSPEC 3991703 B91067520 C91064135 Doc Type: Journal Paper Title: Electronic packaging in the 1990s: the perspective from Europe Authors: Wessely, H.; Fritz, O.; Horn, M.; Klimke, P.; Koschnick, W.; Schmidt, K.-H. Affiliation: Siemens Nixdorf Informationssyst. AG, Munchen, Germany Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 14 Iss: 2 p. 272-84 Date: June 1991 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/91/0600-0272$01.00 Language: English Treatment: Practical Abstract: Electronics packaging and interconnection technologies for mainframe computers are reviewed and predictions about the development of packaging systems beyond 1995 are made. Types of packages, their assembly, wiring board technology, microwiring substrates, polyimide-copper substrates, thin-film technologies, multilayer ceramic technology, printed circuit boards, cooling technology, packaging systems, and European activities are reviewed. These include the RISH project, ESPRIT program, the national microelectronics program (NMP), the APACHIP project, the JESSI program, and the packaging project. (18 Refs.) Classification: B0170J (Product packaging); C5490 (Other aspects of analogue and digital computers); C5420 (Mainframes and minicomputers) Thesaurus: Mainframes; Packaging; Printed circuits Free Terms: Electronics packaging; Interconnection technologies; Mainframe computers; Packaging systems; Assembly; Wiring board technology; Microwiring substrates; Thin-film technologies; Multilayer ceramic technology; Printed circuit boards; Cooling technology; RISH project; ESPRIT program; APACHIP project; JESSI program Item Availability: CD-ROM. INSPEC 3991702 B91067519 Doc Type: Journal Paper Title: Electronic packaging in the 1990s-a perspective from America Authors: Tummala, R.R. Affiliation: IBM Corp., Hopewell Junction, NY, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 14 Iss: 2 p. 262-71 Date: June 1991 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/91/0600-0262$01.00 Language: English Treatment: General/Review; Practical Abstract: The author reviews current packaging technologies. He starts with the packaging environment in the US, then projects the system requirements into the year 2000 and reviews the base packaging technologies currently in use from consumer electronics to mainframe computers. He ends with projected advanced packaging in all the key technologies: chip-level connections, power distribution, and heat removal from the chip, first-level single-chip and multichip packages, package-to-board interconnections, and second-level packages. (17 Refs.) Classification: B0170J (Product packaging) Thesaurus: Cooling; Packaging Free Terms: Packaging technologies; Packaging environment; System requirements; Consumer electronics; Mainframe computers; Chip-level connections; Power distribution; Heat removal; Multichip packages; Package-to-board interconnections; Second-level packages Item Availability: CD-ROM. INSPEC 3991701 B91067518 Doc Type: Journal Paper Title: Electronic packaging in the 1990s-a perspective from Asia Authors: Ohsaki, T. Affiliation: NTT Appl. Electron. Lab., Tokyo, Japan Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 14 Iss: 2 p. 254-61 Date: June 1991 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/91/0600-0254$01.00 Language: English Treatment: General/Review; Practical Abstract: The present status and future trends in electronic packaging technologies are reviewed. Advanced modules packaged with these technologies are shown in three major applications: switching systems, transmission systems, and computer systems. Outlined are VLSI chip interconnection by the tape automated bonding (TAB) method; bump bonding; fine-pitch ceramic flat package suitable for single-chip packaging; multichip packaging using a copper-polyimide substrate for high-speed signal transmission; high-density multilayer printed circuit boards and glass ceramic boards for second-level packaging; and advanced cooling systems. (34 Refs.) Classification: B0170J (Product packaging); B2210 (Printed circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Cooling; Modules; Packaging; Printed circuits; Tape automated bonding; VLSI Free Terms: Electronic packaging technologies; Modules; Switching systems; Transmission systems; Computer systems; VLSI chip interconnection; Tape automated bonding; Bump bonding; Fine-pitch ceramic flat package; Multichip packaging; Signal transmission; Multilayer printed circuit boards; Second-level packaging; Cooling Item Availability: CD-ROM. INSPEC 4916236 B9505-1265Z-004 Doc Type: Conference Paper Title: A 'GaAs on Si' PLL frequency synthesizer IC using chip on chip technology Authors: Sekine, S.; Takada, K.; Suzuki, H.; Kodama, K.; Moriya, S.; Kubota, M. Affiliation: Fujitsu Labs. Ltd., Kanagawa, Japan Conf. Title: Proceedings of the IEEE 1994 Custom Integrated Circuits Conference (Cat. No.94CH3427-2) p. 563-5 Publisher: IEEE New York, NY, USA Date: 1994 670 pp. Country of Publication: USA ISBN: 0 7803 1886 2 CCC: 0 7803 1886 2/94/$3.00 Language: English Conf. Date: 1-4 May 1994 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE/Electron Devices Soc.; IEEE/Solid State Cirucits Council Treatment: Application; Practical; Experimental Abstract: A 'GaAs on Si' PLL frequency synthesizer IC has been developed using chip on chip technology. Chip on chip technology offers refined devices to integrate more than two chips into a single IC package. It is suitable for applications like pagers where small size is the most important factor. The device incorporates a GaAs prescaler as a daughter chip and a CMOS PLL as a mother chip. The power consumption is 6 mW at V/sub DD/=1 V, the operating frequency is 800 MHz. (1 Refs.) Classification: B1265Z (Other digital circuits); B1250 (Modulators, demodulators, discriminators and mixers); B2570D (CMOS integrated circuits); B0170J (Product packaging); B1230 (Signal generators) Thesaurus: CMOS digital integrated circuits; Digital phase locked loops; Elemental semiconductors; Frequency synthesizers; Gallium arsenide; III-V semiconductors; Integrated circuit packaging; Prescalers; Silicon Free Terms: PLL frequency synthesizer IC; Chip on chip technology; GaAs on Si; IC package; Prescaler; Daughter chip; CMOS PLL; Mother chip; Power consumption; Operating frequency; 6 MW; 1 V; 800 MHz; GaAs-Si Numerical Index: Power 6.0E-03 W; Voltage 1.0E+00 V; Frequency 8.0E+08 Hz Chemical Index: GaAs-Si/int GaAs/int As/int Ga/int Si/int GaAs/bin As/bin Ga/bin Si/el Item Availability: CD-ROM. INSPEC 4432494 B9308-2220J-004 Doc Type: Conference Paper Title: Effect of molding compound thermal conductivity on thermal performance of molded multi-chip modules Authors: Azar, K.; Mandrone, C.D.; Segelken, J.M. Affiliation: AT&T Bell Lab., Andover, MA, USA Conf. Title: Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.93CH3226-8) p. 19-27 Publisher: IEEE New York, NY, USA Date: 1993 x+214 pp. Country of Publication: USA ISBN: 0 7803 0863 8 CCC: 0 7803 0863 8/93/$3.00 Language: English Conf. Date: 2-4 Feb. 1993 Conf. Loc: Austin, TX, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: Exploratory work has been carried out to investigate filled epoxy systems for thermal management enhancements for plastic encapsulated integrated circuits. A computational study was conducted to examine the effect of molding compound thermal conductivity on thermal resistance of a molded multi-chip module. Seven different molding thermal conductivities were considered. The air velocity was varied from natural convection to high-velocity forced convection. The results showed that an eight-fold increase in molding compound thermal conductivity reduces the junction-to-ambient thermal resistance by 20% in natural convection and by 54% in high-velocity forced convection. (9 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging) Thesaurus: Convection; Cooling; Multichip modules Free Terms: Molding compound thermal conductivity; Thermal performance; Molded multi-chip modules; Filled epoxy systems; Thermal management enhancements; Plastic encapsulated integrated circuits; Air velocity; Natural convection; High-velocity forced convection; Thermal conductivity; Junction-to-ambient thermal resistance Item Availability: CD-ROM. INSPEC 4288299 B9301-2220J-005 C9301-5440-006 Doc Type: Journal Paper Title: Ultra-Dense: an MCM-based 3-D digital signal processor Authors: Segelken, J.M.; Wu, L.J.; Lau, M.Y.; Tai, K.L.; Shively, R.R.; Grau, T.G. Affiliation: AT&T Bell Labs., Murray Hill, NJ, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 15 Iss: 4 p. 438-43 Date: Aug. 1992 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/92/$03.00 Language: English Treatment: General/Review; Practical; Product review Abstract: The DSP3 Multiprocessor Project has produced a multi-GFLOP machine that is applicable to a variety of signal processing and pattern recognition problems. A companion program, the Ultra-Dense Project, is utilizing silicon-on-silicon multichip module (MCM) technology and innovative advanced packaging and physical design to achieve a parallel three-dimensional digital signal processor based on the DSP3. The authors present an overview and outline systems architecture the micro-interconnect technology (Si-on-Si MCM), and advances in physical design and packaging technology leading to an ultra-dense project demonstration. (4 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging); C5440 (Multiprocessing systems); C5220P (Parallel architecture) Thesaurus: Multichip modules; Packaging; Parallel architectures; Parallel machines Free Terms: Parallel processors; 3-D digital signal processor; DSP3; Multiprocessor Project; Multi-GFLOP machine; Ultra-Dense Project; Overview; Systems architecture; Micro-interconnect technology; Si-on-Si MCM; Physical design; Packaging technology; Ultra-dense project demonstration; Si-Si modules Chemical Index: Si-Si/int Si/int Si/el Item Availability: CD-ROM. INSPEC 5241818 B9605-4270-028 Doc Type: Conference Paper Title: Passive optical alignment of stacked multi-fiber tapes to a two-dimensional surface-emitting laser array Authors: Matsuda, K.; Chino, T.; Yoshida, T.; Kobayashi, Y.; Hatada, K. Affiliation: Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan Conf. Title: International Electron Devices Meeting. Technical Digest (Cat. No.95CH35810) p. 587-90 Publisher: IEEE New York, NY, USA Date: 1995 1026 pp. Country of Publication: USA ISBN: 0 7803 2700 4 CCC: 0 7803 2700 4/96/$4.00 Language: English Conf. Date: 10-13 Dec. 1995 Conf. Loc: Washington, DC, USA Conf. Sponsor: IEEE Electron. Devices Soc Treatment: Practical; Experimental Abstract: A simple method of coupling parallel fibers to a surface-emitting laser (SEL) array is proposed and demonstrated. The SEL chip has guiding holes on the backside which are aligned precisely to the SEL mesas on the front side. Simply inserting fibers to the guiding holes, optical coupling can be achieved. Three fiber tapes each of which includes four fibers are coupled to a 4*3 SEL array. Average coupling efficiency of 35.0% is obtained. (10 Refs.) Classification: B4270 (Integrated optoelectronics); B4125 (Fibre optics); B4320J (Semiconductor lasers); B4320L (Laser resonators and cavities) Thesaurus: Optical fibre couplers; Optical interconnections; Semiconductor laser arrays; Surface emitting lasers Free Terms: Passive optical alignment; Stacked multi-fiber tapes; Two-dimensional surface-emitting laser array; Parallel fibers; SEL mesas; Optical coupling; Coupling efficiency; 35.0 Percent Numerical Index: Efficiency 3.5E+01 percent Item Availability: CD-ROM. INSPEC 5213622 B9605-2250-003 Doc Type: Journal Paper Title: Design and evaluation of an epoxy three-dimensional multichip module Authors: Stern, J.M.; Larcombe, S.P.; Ivey, P.A.; Seed, L.; Shelley, A.J.; Goodenough, N.J. Affiliation: Electron. Syst. Group, Sheffield Univ., UK Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 19 Iss: 1 p. 188-94 Publisher: IEEE Date: Feb. 1996 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/96/$05.00 Language: English Treatment: Application; Practical; Experimental Abstract: A low-cost, three-dimensional multichip module (MCM) technology provides greatly improved system density and reduced mass over planar packaging technologies. The technology offers a high degree of testability that negates the need for known good die (KGD) procurement. Testing is achieved with very low cost overheads and with no increase in the volume of the module. The technology allows complete, heterogeneous systems to be packaged and interconnected in a single, ultra-dense module. The electrical characteristics of the technology are comparable to standard chip packages. However, the parasitics due to package-to-package interconnects are eliminated. This removes the dominant cause of parasitics, dramatically improving the electrical characteristics. A programmable integrated camera and image processing system has been developed which incorporates a grayscale camera, analog-to-digital conversion, four programmable processors and memory. Utilizing the three-dimensional multichip module technology, the system, which consists of nine chips and 36 discrete components, has an overall volume of 4.77 ml. This is approximately six times more dense than an advanced PCB implementation. The system forms the first stage in the design and manufacture of a portable video communications device. For such applications, low system volume and mass are key attributes. The system demonstrates the potential of the packaging technique for the integration of complete mixed signal systems incorporating sensors and processing. Further developments to the technology will provide increased module density, improved routing capacity, and electrical performance. (10 Refs.) Classification: B2250 (Multichip modules); B0170J (Product packaging); B6430H (Video recording) Thesaurus: Image processing equipment; Integrated circuit packaging; Multichip modules; Video cameras Free Terms: Epoxy three-dimensional multichip module; System density; Low cost test overheads; Heterogeneous systems; Ultra-dense module; Electrical characteristics; Programmable integrated camera; Portable video communications device; System volume; Packaging technique; Mixed signal systems; Outing capacity Item Availability: CD-ROM. INSPEC 5197743 A9607-4280L-014 B9604-4130-017 Doc Type: Journal Paper Title: Analysis of antireflection coatings using the FD-TD method with the PML absorbing boundary condition Authors: Yamauchi, J.; Mita, M.; Aoki, S.; Nakano, H. Affiliation: Coll. of Eng., Hosei Univ., Tokyo, Japan Journal: IEEE Photonics Technology Letters Vol: 8 Iss: 2 p. 239-41 Publisher: IEEE Date: Feb. 1996 Country of Publication: USA ISSN: 1041-1135 CODEN: IPTLEL CCC: 1041-1135/96/$05.00 Language: English Treatment: Theoretical/Mathematical Abstract: A step-index optical waveguide with an antireflection coating is analyzed using the finite-difference time-domain (FD-TD) method combined with the perfectly matched layer absorbing boundary condition (PML-ABC). It is demonstrated that the numerical simulations having a dynamic range over that for the Mur absorbing boundary condition can be obtained for a single-layer coating. The analysis of a double-layer coating reveals the transient behavior of reflected fields. (17 Refs.) Classification: A4280L (Optical waveguides and couplers); A7820D (Optical constants and parameters); B4130 (Optical waveguides); B5240D (Waveguide and cavity theory) Thesaurus: Antireflection coatings; Finite difference time-domain analysis; Optical films; Optical waveguide theory; Reflectivity; Refractive index Free Terms: FD-TD method; PML absorbing boundary condition; Antireflection coatings; Step-index optical waveguide; Finite-difference time-domain method; Perfectly matched layer absorbing boundary condition; Numerical simulations; Dynamic range; Mur absorbing boundary condition; Single-layer coating; Double-layer coating; Reflected field transient behaviour Item Availability: CD-ROM. INSPEC 5188886 B9603-6250F-169 Doc Type: Conference Paper Title: Two methods for estimating the diversity characteristics of built-in antennas for mobile communication equipment Authors: Maeda, T.; Sekine, S.; Obayashi, S.; Morooka, T. Affiliation: Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan Conf. Title: IEEE Antennas and Propagation Society International Symposium. 1995 Digest (Cat. No.95CH35814) p. 1944-7 vol.4 Publisher: IEEE New York, NY, USA Date: 1995 4 vol. viii+2160 pp. Country of Publication: USA ISBN: 0 7803 2719 5 CCC: 0 7803 2719 5/95/$4.00 Language: English Conf. Date: 18-23 June 1995 Conf. Loc: Newport Beach, CA, USA Treatment: Practical; Experimental Abstract: In mobile communications, the diversity technique plays a very important role in improving the quality of digital transmissions, and the fading simulator is widely employed to achieve a quasi-fading environment. However, the fading simulator cannot be used to evaluate the effects of the antenna radiation patterns on the diversity characteristics. It is very difficult to predict analytically the radiation characteristics of built-in antennas in portable radio equipment, because they are affected by nearby electrical devices. Therefore, an experimental investigation is important. We proposed two measurement systems for evaluating the radiation characteristics of built-in antennas for hand-held radio equipment. Two methods for estimating the diversity characteristics of mobile communication equipment using these two measurement systems are presented. (4 Refs.) Classification: B6250F (Mobile radio systems); B5270 (Antennas); B7210 (Instrumentation and measurement systems) Thesaurus: Antenna radiation patterns; Antenna testing; Diversity reception; Land mobile radio; Measurement systems; Mobile antennas; Mobile radio Free Terms: Diversity characteristics; Built-in antennas; Mobile communication equipment; Digital transmissions; Fading simulator; Antenna radiation patterns; Portable radio equipment; Electrical devices; Experimental investigation; Measurement systems; Hand-held radio equipment Item Availability: CD-ROM. INSPEC 5158269 B9602-2250-007 Doc Type: Journal Paper Title: Utilizing a low cost 3D packaging technology for consumer applications Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, L. Affiliation: Dept. of Electron. & Electr. Eng., Sheffield Univ., UK Journal: IEEE Transactions on Consumer Electronics Vol: 41 Iss: 4 p. 1095-102 Publisher: IEEE Date: Nov. 1995 Country of Publication: USA ISSN: 0098-3063 CODEN: ITCEDA CCC: 0098-3063/95/$04.00 Language: English Treatment: Application; New development; Practical Abstract: This paper demonstrates how a low cost three-dimensional packaging (multichip module-vertical) technology can be utilized to implement systems for consumer applications. In any application where system cost, volume and mass are important, this packaging technique can be advantageous, particularly in the rapidly growing portable electronics industry. To illustrate this we present a general-purpose, low-cost camera and image processing system in the new packaging technology. This can be used in multimedia, surveillance and smart vision applications. (7 Refs.) Classification: B2250 (Multichip modules); B6210R (Multimedia communications); B6140C (Optical information, image and video signal processing); B7230 (Sensing devices and transducers); B6430H (Video recording); B0170J (Product packaging) Thesaurus: Consumer electronics; Image processing; Intelligent sensors; Multichip modules; Multimedia systems; Surveillance; Video cameras Free Terms: Low cost 3D packaging technology; Consumer applications; System cost; Volume; Mass; Portable electronics industry; Low-cost camera; Image processing system; Smart vision applications; Surveillance applications; Multimedia applications; Multichip module-vertical; Portable video communicator Item Availability: CD-ROM. INSPEC 5137796 B9601-8150-007 C9601-3340H-122 Doc Type: Conference Paper Title: Power system disturbance monitoring using spectral analysis techniques Authors: O'Shea, P.; Palmer, E.; Frazer, G. Affiliation: Dept. of Commun. & Electr. Eng., R. Melbourne Inst. of Technol., Vic., Australia Conf. Title: 1995 International Conference on Acoustics, Speech, and Signal Processing. Conference Proceedings (Cat. No.95CH35732) p. 2731-4 vol.4 Publisher: IEEE New York, NY, USA Date: 1995 5 vol. 3662 pp. Country of Publication: USA ISBN: 0 7803 2431 5 CCC: 0 7803 2431 5/94/$4.00 Language: English Conf. Date: 9-12 May 1995 Conf. Loc: Detroit, MI, USA Conf. Sponsor: Signal Process. Soc. IEEE Treatment: Theoretical/Mathematical; Experimental Abstract: This paper considers the problem of measuring and analysing the frequency and phase angle variations which occur in a power system after a fault or disturbance. This is an important problem because the results of the analysis are used in implementing control strategies to avert generator cutout. Commonly, the frequency is not measured directly, but is inferred from the instantaneous power at the substation. Since there is a complicated non-linear relationship between the power and the frequency, some bias is incurred in the measurement. This paper proposes instead that the angle and or frequency be obtained directly via an analytic signal readily constructed from the 3-phase output of the power system. The paper also proposes enhancements for some of the currently employed signal analysis techniques, and a new technique based on an extension of Thompson's (1982) harmonic line test. (9 Refs.) Classification: B8150 (Power system measurement and metering); B8375 (Substations); B7310H (Phase and gain measurement); B7310G (Frequency measurement); B8110B (Power system management, operation and economics); B6140 (Signal processing and detection); C3340H (Control of electric power systems) Thesaurus: Frequency measurement; Phase measurement; Power system control; Power system harmonics; Power system measurement; Spectral analysis; Substations Free Terms: Power system disturbance monitoring; Spectral analysis; Phase angle variations measurement; Frequency variations measurement; Control strategies; Generator cutout; Instantaneous power; Substation; Measurement bias; Analytic signal; 3-Phase output; Signal analysis techniques; Thompson's harmonic line test Item Availability: CD-ROM. INSPEC 5131841 B9601-6140C-370 Doc Type: Conference Paper Title: An ultra compact, low-cost, complete image-processing system Authors: Stem, J.M.; Ivey, P.A.; Larcombe, S.P.; Goodenough, N.J.; Seed, N.L.; Shelley, A.J. Affiliation: Sheffield Univ., UK Conf. Title: 1995 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.95CH35753) p. 230-1 Editors: Wuorinen, J.H. Publisher: IEEE New York, NY, USA Date: 1995 440 pp. Country of Publication: USA ISBN: 0 7803 2495 1 CCC: 0 7803 2495 1/95/$4.00 Language: English Conf. Date: 15-17 Feb. 1995 Conf. Loc: San Francisco, CA, USA Treatment: Practical Abstract: A low-cost, three-dimensional MCM technology, referred to as MCM-Vertical, or MCM-V gains an order of magnitude improvement in the volume efficiency of a system. An integrated camera and image-processing system forms the core module for a portable video communications system that could transmit compressed video over personal communications networks, such as GSM. (3 Refs.) Classification: B6140C (Optical information, image and video signal processing); B2250 (Multichip modules); B6250F (Mobile radio systems) Thesaurus: Multichip modules; Personal communication networks; Video signal processing Free Terms: Ultra compact low-cost technology; Three-dimensional MCM; MCM-Vertical; MCM-V; Volume efficiency; Integrated system; Portable video communications; Video compression; Personal communications networks; GSM; Camera; Image processing Item Availability: CD-ROM. INSPEC 5119306 B9601-0170E-003 Doc Type: Conference Paper Title: A new approach for the selection of test points for fault diagnosis Authors: El-Gamal, M.A.; Hassan, A.S.O.; Abdel-Malek, H.L. Affiliation: Dept. of Eng. Phys. & Math., Cairo Univ., Giza, Egypt Conf. Title: 1995 IEEE Symposium on Circuits and Systems (Cat. No.95CH35771) p. 2019-22 vol.3 Publisher: IEEE New York, NY, USA Date: 1995 3 vol. l+2346 pp. Country of Publication: USA ISBN: 0 7803 2570 2 CCC: 0 7803 2570 2/95/$4.00 Language: English Conf. Date: 28 April-3 May 1995 Conf. Loc: Seattle, WA, USA Conf. Sponsor: IEEE Circuits & Syst. Soc Treatment: Theoretical/Mathematical Abstract: A new criterion and an efficient algorithm for the selection of test points in multifrequency fault diagnosis of linear circuits are presented. The proposed criterion exploits the biquadratic nature of the response in terms of circuit parameters instead of the common use of first order sensitivities. Accordingly it is capable of handling catastrophic faults. Employing the proposed criterion, an efficient two-phase fault diagnosis algorithm is introduced. The first phase selects a set of test points and characterizes the response for possible faults. This is done without the simulation of a preselected set of faults. The second phase efficiently isolates on-line actual faults using test points without any computation. A test example is presented to demonstrate the effectiveness of the proposed criterion and algorithm. (10 Refs.) Classification: B0170E (Production facilities and engineering); B7210B (Automatic test and measurement systems) Thesaurus: Analogue circuits; Automatic testing; Circuit testing; Fault diagnosis Free Terms: Test points selection; Analog circuits; Multifrequency fault diagnosis; Linear circuits; Circuit parameters; Two-phase fault diagnosis algorithm Item Availability: CD-ROM. INSPEC 5118478 C9601-5230-006 Doc Type: Conference Paper Title: Algorithms for arithmetic operation in a systolic array of single-bit processor (SASP) Authors: Malek, H. Affiliation: Res. & Dev. Div., Lockheed Missiles & Space Co. Inc., Palo Alto, CA, USA Conf. Title: 1995 Proceedings. Seventh Annual IEEE International Conference on Wafer Scale Integration (Cat. No.95CH3574-2) p. 359-70 Publisher: IEEE New York, NY, USA Date: 1995 ix+382 pp. Country of Publication: USA ISBN: 0 7803 2467 6 CCC: 0 7803 2466 8/95/$4.00 Language: English Conf. Date: 18-20 Jan. 1995 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Comput. Soc.; IEEE Components, Packaging, & Manuf. Technol. Soc Treatment: Practical Abstract: Algorithms for binary integer arithmetic in a Systolic Array of Single-bit Processor (SASP), designed for implementation in wafer scale integration (WSI), are presented. The processing elements (PE), operated in a Single instruction Multiple Data (SIMD) mode, each contains a single-bit arithmetic and logic unit (ALU). The salient feature of the developed algorithms is in the use of the primitive ALU functions to achieve data dependent division arithmetic operational in the SIMD machine. Also, the innovative and efficient algorithmic use of the single-bit ALUs in the SIMD environment makes it possible to realize the full performance of the massively parallel processor. The algorithms are described by a set of programming flow charts. The required sequence of operations in each algorithm are presented according to the actual SASP mnemonics for the operational (OP) codes. (3 Refs.) Classification: C5230 (Digital arithmetic methods); C5220P (Parallel architecture); C4240P (Parallel programming and algorithm theory) Thesaurus: Digital arithmetic; Parallel algorithms; Systolic arrays; Wafer-scale integration Free Terms: Arithmetic operation; Systolic array; Single-bit processor; Binary integer arithmetic; Wafer scale integration; SIMD mode; Single instruction multiple data mode; Massively parallel processor; WSI Item Availability: CD-ROM. INSPEC 5118462 B9601-1265F-015 C9601-5440-010 Doc Type: Conference Paper Title: An experimental fault-tolerant active substrate MPC MCM using standard gate array technology Authors: Hedge, S.J.; Hall, C.J.; Habiger, C.M.; Lea, R.M. Affiliation: Aspex Microsyst., Brunel Univ., Uxbridge, UK Conf. Title: 1995 Proceedings. Seventh Annual IEEE International Conference on Wafer Scale Integration (Cat. No.95CH3574-2) p. 197-206 Publisher: IEEE New York, NY, USA Date: 1995 ix+382 pp. Country of Publication: USA ISBN: 0 7803 2467 6 CCC: 0 7803 2466 8/95/$4.00 Language: English Conf. Date: 18-20 Jan. 1995 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Comput. Soc.; IEEE Components, Packaging, & Manuf. Technol. Soc Treatment: Practical; Experimental Abstract: The Massively Parallel Computing (MPC) arena continues to demand ever more powerful and compact building-blocks, especially for the construction of embedded-MPC systems. Multi-Chip Modules (MCMs) offer a means of implementing such building-blocks, but have been shown to suffer from cost and delivery problems at the complexity levels required. As these problems stem from infant die mortality, assembly yield losses and the 'known-good-die' problem it has been proposed to incorporate fault-tolerance into an MCM to permit these faults to be overcome by programmable MCM configuration, rather than costly and time-consuming module re-work. Theoretical studies have confirmed the potential of this approach, but it remains to evaluate practical means of its implementation. The present paper reports the results of an initial practical experiment into the design of such an MPC MCM that uses a fault-tolerant active substrate based on an existing gate-array wafer. (5 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2250 (Multichip modules); C5440 (Multiprocessing systems); C5220P (Parallel architecture); C5470 (Performance evaluation and testing) Thesaurus: Fault tolerant computing; Multichip modules; Parallel architectures; Parallel machines; Programmable logic arrays Free Terms: Fault-tolerant active substrate MCM; Standard gate array technology; Massively parallel computing; Multichip modules; Infant die mortality; Assembly yield losses; Known-good-die problem; Programmable MCM configuration; Gate-array wafer Item Availability: CD-ROM. INSPEC 5044718 C9510-3360D-008 Doc Type: Conference Paper Title: Application of fuzzy neural network control to automatic train operation and tuning of its control rules Authors: Sekine, S.; Imasaki, N.; Endo, T. Affiliation: Syst. & Software Eng. Lab., Toshiba Corp., Kawasaki, Japan Conf. Title: Proceedings of 1995 IEEE International Conference on Fuzzy Systems. The International Joint Conference of the Fourth IEEE International Conference on Fuzzy Systems and The Second International Fuzzy Engineering Symposium (Cat. No.95CH35741) p. 1741-6 vol.4 Publisher: IEEE New York, NY, USA Date: 1995 5 vol. (xxxiv+2342+vii+106 pp.) Country of Publication: USA ISBN: 0 7803 2461 7 CCC: 0 7803 2461 7/94/$4.00 Language: English Conf. Date: 20-24 March 1995 Conf. Loc: Yokohama, Japan Conf. Sponsor: IEEE Neural Networks Council; Lab. Int. Fuzzy Eng. Res.; Japan Soc. Fuzzy Theory & Syst.; Japan Inf. Process. Dev. Center Treatment: Theoretical/Mathematical; Experimental Abstract: We have proposed two-degree-of-freedom fuzzy neural network control systems. It has a hierarchical structure of two sets of control knowledge, thus it is easy to extract and refine fuzzy rules before and after the operation has started, and the number of fuzzy rules is reduced. This paper shows an example application of automatic train operation and presents a rule tuning method. (7 Refs.) Classification: C3360D (Rail-traffic system control); C1230D (Neural nets); C1340F (Fuzzy control); C1340B (Multivariable control systems); C1340N (Neurocontrol) Thesaurus: Fuzzy control; Fuzzy neural nets; Hierarchical systems; Neurocontrollers; Railways Free Terms: Fuzzy neural network control; Automatic train operation; Control rules tuning; Hierarchical control structure; Fuzzy control; Railways Item Availability: CD-ROM. INSPEC 5032648 C9510-3360D-004 Doc Type: Conference Paper Title: Application of fuzzy neural network control to automatic train operation Authors: Sekine, S.; Nishimura, M. Affiliation: Toshiba Corp., Kawasaki, Japan Conf. Title: Proceedings of 1995 IEEE International Conference on Fuzzy Systems. The International Joint Conference of the Fourth IEEE International Conference on Fuzzy Systems and The Second International Fuzzy Engineering Symposium (Cat. No.95CH35741) p. 39-40 vol.5 Publisher: IEEE New York, NY, USA Date: 1995 5 vol. (xxxiv+2342+vii+106 pp.) Country of Publication: USA ISBN: 0 7803 2461 7 CCC: 0 7803 2461 7/94/$4.00 Language: English Conf. Date: 20-24 March 1995 Conf. Loc: Yokohama, Japan Conf. Sponsor: IEEE Neural Networks Council; Lab. Int. Fuzzy Eng. Res.; Japan Soc. Fuzzy Theory & Syst.; Japan Inf. Process. Dev. Center Treatment: Experimental Abstract: A transit system is subject to widely varying external conditions, such as weather, the time of day, etc. Different situations imply different control purposes and the varying conditions induce fluctuating dynamic characteristics. Therefore it is difficult to automatically control the vehicle satisfactorily. We apply a two-degree-of-freedom fuzzy neural network control system to automate the vehicle operation. The controller's function is to accurately stop the vehicle at a station. We investigate the controller's performance with acceleration error due to changing dynamic characteristics and with a control purpose transition from velocity control to position control. (0 Refs.) Classification: C3360D (Rail-traffic system control); C1340F (Fuzzy control); C1230D (Neural nets); C3120E (Velocity, acceleration and rotation control); C3120C (Spatial variables control); C1340N (Neurocontrol) Thesaurus: Fuzzy control; Fuzzy neural nets; Intelligent control; Position control; Railways; Velocity control Free Terms: Fuzzy neural network control; Automatic train operation; Transit system; Acceleration error; Velocity control; Position control Item Availability: CD-ROM. INSPEC 5022802 B9509-7220-019 C9509-5530-017 Doc Type: Conference Paper Title: A micro-packaged image acquisition and processing module Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, N.L.; Shelley, A.J. Affiliation: Sheffield Univ., UK Conf. Title: Fifth International Conference on Image Processing and its Applications (Conf. Publ. No.410) p. 455-9 Publisher: IEE London, UK Date: 1995 xxii+857 pp. Country of Publication: UK ISBN: 0 85296 642 3 Language: English Conf. Date: 4-6 July 1995 Conf. Loc: Edinburgh, UK Treatment: Practical Abstract: The paper describes a prototype module, which is an image acquisition and processing pipeline implemented in a micro-package. The module converts incident light directly to processed digital video data. The system is packaged using a novel three-dimensional technology called MCM-V (multichip module-vertical), Val (1991). This technology stacks integrated circuits in the z-axis to produce dense systems. The module is fully programmable and can be used in a wide range of image processing tasks. The results presented form the first stage in the development of high performance ultra-miniature camera and image processing systems. (8 Refs.) Classification: B7220 (Signal processing and conditioning equipment and techniques); B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B2250 (Multichip modules); B6430H (Video recording); C5530 (Pattern recognition and computer vision equipment); C5135 (Digital signal processing chips); C5220P (Parallel architecture) Thesaurus: Application specific integrated circuits; Digital signal processing chips; Image processing equipment; Multichip modules; Parallel architectures; Pipeline processing; Transputers; Video cameras; Video signal processing; VLSI Free Terms: Micro-packaged image acquisition; Processing module; Prototype module; Processed digital video data; Three-dimensional technology; MCM-V; Multichip module-vertical; Integrated circuits; Z-axis; Dense systems; Fully programmable module; High performance ultra-miniature camera Item Availability: CD-ROM. INSPEC 5009789 B9509-0170G-005 Doc Type: Conference Paper Title: New solderless connection technology using light-setting insulation resin Authors: Nagao, K.; Nishihara, K.; Fujimoto, H.; Hatada, K. Affiliation: Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan Conf. Title: Sixteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Low-Cost Manufacturing Technologies for Tomorrow's Global Economy'. Proceedings 1994 IEMT Symposium (Cat. No.94CH3473-6) p. 15-19 vol.1 Publisher: IEEE New York, NY, USA Date: 1994 2 vol. (xii+404+viii+104 pp.) Country of Publication: USA ISBN: 0 7803 2037 9 CCC: 0 7803 2037 9/94/$3.00 Language: English Conf. Date: 12-14 Sept. 1994 Conf. Loc: La Jolla, CA, USA Conf. Sponsor: Electron. Ind. Assoc.; IEEE Components Packaging & Manuf. Technol. Soc Treatment: New development; Practical; Experimental Abstract: A new solderless connection technology using light-setting insulation resin has been developed. This makes possible fine-pitch and short length connection between the FPC (Flexible Printed Circuit) and the electrodes of an electronic device. An FPC is attached by the adhesive force of the light-setting insulation resin. This technology has been applied to a thin-film magnetic head, and realized ultra fine connection, i.e. a connection pitch of 75 mu m (present ratio 1/2) and a connection length of 250 mu m (present ratio 1/10). (0 Refs.) Classification: B0170G (General fabrication techniques); B3120N (Magnetic thin film devices); B3120B (Magnetic recording ); B2210F (Printed circuit accessories); B0560 (Polymers and plastics (engineering materials science)); B0170J (Product packaging) Thesaurus: Adhesion; Fine-pitch technology; Joining processes; Magnetic heads; Magnetic thin film devices; Organic insulating materials; Polymer films; Printed circuit accessories Free Terms: Solderless connection technology; Light-setting insulation resin; Fine-pitch connection; Short length connection; Flexible printed circuit connection; Electronic device electrodes; Adhesive force; Thin-film magnetic head; Ultra fine connection; Connection pitch; Connection length; UV irradiation energy level; V-I characteristics; Humidity test; 75 Mum; 250 Mum Numerical Index: Size 7.5E-05 m; Size 2.5E-04 m Item Availability: CD-ROM. INSPEC 4916310 A9508-8770F-033 B9505-7510D-036 Doc Type: Conference Paper Title: Multiresolution wavelet analysis of ECG during ischemia and reperfusion Authors: Thakor, N.; Gramatikov, B.; Mita, M. Affiliation: Johns Hopkins Univ., Baltimore, MD, USA Conf. Title: Proceedings. Computers in Cardiology 1993 (Cat. No.93CH3384-5) p. 895-8 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1993 xxviii+911 pp. Country of Publication: USA ISBN: 0 8186 5470 8 CCC: 0276-6547/93/$3.00 Language: English Conf. Date: 5-8 Sept. 1993 Conf. Loc: London, UK Conf. Sponsor: IEEE Treatment: Experimental Abstract: ECGs from ischemic animals were analysed using multiresolution wavelets of G.S. Mallat (IEEE Trans. Pattern Anal., Machine Intell., vol. 11, no. 7, p. 674-93, 1989). The authors propose a new way, based on the detail signals D/sub 2j/f, for detecting injury related changes in the ECG. Analyses of experimental data reveal a short-term increase of magnitude in scales corresponding to the medium frequency components during occlusion of coronary vessels. (5 Refs.) Classification: A8770F (Electrodiagnostics); A8730C (Electrical activity in neurophysiological processes); B7510D (Bioelectric signals); B6140 (Signal processing and detection) Thesaurus: Electrocardiography; Medical signal processing; Wavelet transforms Free Terms: Multiresolution wavelet analysis; Reperfusion; Ischemia; ECG analysis; Detail signals; D/sub 2j/f; Injury related changes detection; Dog experiments; Coronary vessels occlusion; Medium frequency components; Ischemic animals Item Availability: CD-ROM. INSPEC 4916236 B9505-1265Z-004 Doc Type: Conference Paper Title: A 'GaAs on Si' PLL frequency synthesizer IC using chip on chip technology Authors: Sekine, S.; Takada, K.; Suzuki, H.; Kodama, K.; Moriya, S.; Kubota, M. Affiliation: Fujitsu Labs. Ltd., Kanagawa, Japan Conf. Title: Proceedings of the IEEE 1994 Custom Integrated Circuits Conference (Cat. No.94CH3427-2) p. 563-5 Publisher: IEEE New York, NY, USA Date: 1994 670 pp. Country of Publication: USA ISBN: 0 7803 1886 2 CCC: 0 7803 1886 2/94/$3.00 Language: English Conf. Date: 1-4 May 1994 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE/Electron Devices Soc.; IEEE/Solid State Cirucits Council Treatment: Application; Practical; Experimental Abstract: A 'GaAs on Si' PLL frequency synthesizer IC has been developed using chip on chip technology. Chip on chip technology offers refined devices to integrate more than two chips into a single IC package. It is suitable for applications like pagers where small size is the most important factor. The device incorporates a GaAs prescaler as a daughter chip and a CMOS PLL as a mother chip. The power consumption is 6 mW at V/sub DD/=1 V, the operating frequency is 800 MHz. (1 Refs.) Classification: B1265Z (Other digital circuits); B1250 (Modulators, demodulators, discriminators and mixers); B2570D (CMOS integrated circuits); B0170J (Product packaging); B1230 (Signal generators) Thesaurus: CMOS digital integrated circuits; Digital phase locked loops; Elemental semiconductors; Frequency synthesizers; Gallium arsenide; III-V semiconductors; Integrated circuit packaging; Prescalers; Silicon Free Terms: PLL frequency synthesizer IC; Chip on chip technology; GaAs on Si; IC package; Prescaler; Daughter chip; CMOS PLL; Mother chip; Power consumption; Operating frequency; 6 MW; 1 V; 800 MHz; GaAs-Si Numerical Index: Power 6.0E-03 W; Voltage 1.0E+00 V; Frequency 8.0E+08 Hz Chemical Index: GaAs-Si/int GaAs/int As/int Ga/int Si/int GaAs/bin As/bin Ga/bin Si/el Item Availability: CD-ROM. INSPEC 4876909 A9505-4282-004 B9503-4140-020 Doc Type: Journal Paper Title: 4*4 InGaAlAs/lnAlAs MQW directional coupler waveguide switch modules integrated with spot-size converters and their 10 Gbit/s operation Authors: Kawano, K.; Sekine, S.; Takeuchi, H.; Wada, M.; Kohtoku, M.; Yoshimoto, N.; Ito, T.; Yanagibashi, M.; Kondo, S.; Noguchi, Y. Affiliation: NTT Opto-Electron. Labs., Kanagawa, Japan Journal: Electronics Letters Vol: 31 Iss: 2 p. 96-7 Date: 19 Jan. 1995 Country of Publication: UK ISSN: 0013-5194 CODEN: ELLEAK CCC: 0013-5194/94/$10.00 Language: English Treatment: Application; Practical Abstract: 4*4 InGaAlAs/InAlAs MQW directional coupler waveguide switch modules integrated with spot-size converters are developed for the first time. Because the switching time is sufficiently short (<70 ps, which is limited by the driver speed), no bits are lost during a 10 Gbit/s switching experiment at 1.55 mu m wavelength. (8 Refs.) Classification: A4282 (Integrated optics); A4280L (Optical waveguides and couplers); A4280S (Optical communications devices); B4140 (Integrated optics); B4130 (Optical waveguides); B4150 (Electro-optical devices); B6260 (Optical links and equipment); B6230H (Photonic switching systems) Thesaurus: Aluminium compounds; Digital communication; Electro-optical switches; Gallium arsenide; Gallium compounds; III-V semiconductors; Indium compounds; Integrated optics; Modules; Optical directional couplers; Optical waveguides; Photonic switching systems; Semiconductor quantum wells Free Terms: MQW optical waveguide switch; Directional coupler waveguide switch; Spot-size converters; 4*4 Switch modules; 10 Gbit/s; 70 Ps; 1.55 Micron; InGaAlAs-InAlAs Numerical Index: Bit rate 1.0E+10 bit/s; Time 7.0E-11 s; Wavelength 1.55E-06 m Chemical Index: InGaAlAs-InAlAs/int InGaAlAs/int InAlAs/int Al/int As/int Ga/int In/int InGaAlAs/ss InAlAs/ss Al/ss As/ss Ga/ss In/ss Item Availability: CD-ROM. INSPEC 4875080 B9503-7230G-041 C9503-5530-011 Doc Type: Conference Paper Title: An ultra-miniature camera and processing system Authors: Larcombe, S.P.; Stern, J.M.; Ivey, P.A.; Seed, N.L. Affiliation: Dept. of Electron. & Electr. Eng., Sheffield Univ., UK Conf. Title: IEE Colloquium on 'Integrated Imaging Sensors and Processing' (Digest No.1994/238) p. 4/1-6 Publisher: IEE London, UK Date: 1994 41 pp. Country of Publication: UK Language: English Conf. Date: 5 Dec. 1994 Conf. Loc: London, UK Conf. Sponsor: IEE Treatment: Practical Abstract: The following paper describes a single module which integrates an image sensor and programmable processing resources. The completed module has dimensions of 20.6(w)*15.75(d)*14.7(h) mm, giving an overall volume of 4.75 ml (0.3 cubic inches). This is achieved using a novel three-dimensional packaging technology, referred to as MCM-V (multichip module-vertical). We have demonstrated that this technique can be applied to produce high-density systems incorporating sensors, processing and support circuitry. The technology, system architecture and applications are discussed. (3 Refs.) Classification: B7230G (Image sensors); B7220 (Signal processing and conditioning equipment and techniques); B6140C (Optical information, image and video signal processing); C5530 (Pattern recognition and computer vision equipment) Thesaurus: Cameras; Image processing equipment; Image sensors Free Terms: Ultra-miniature camera; Programmable processing resources; Image sensor; Three-dimensional packaging technology; MCM-V; Multichip module-vertical packaging; High-density systems; 20.6 Mm; 15.75 Mm; 14.7 Mm Numerical Index: Size 2.06E-02 m; Size 1.575E-02 m; Size 1.47E-02 m Item Availability: CD-ROM. INSPEC 4831124 A9501-4282-002 B9501-4150-002 Doc Type: Journal Paper Title: Dynamic response of 2*2 InGaAlAs/InAlAs multiquantum well (MQW) directional coupler waveguide switch modules Authors: Ito, T.; Kohtoku, M.; Yoshimoto, N.; Kawano, K.; Sekine, S.; Yanagibashi, M.; Kondo, S. Affiliation: Nippon Telegraph & Telephone Corp., NTT Opto-Electron. Labs., Kanagawa, Japan Journal: Electronics Letters Vol: 30 Iss: 23 p. 1936-7 Date: 10 Nov. 1994 Country of Publication: UK ISSN: 0013-5194 CODEN: ELLEAK CCC: 0013-5194/94/$7.50+0.00 Language: English Treatment: Practical; Experimental Abstract: The first dynamic response of fully packaged 2*2 InGaAlAs/InAlAs MQW directional coupler waveguides with spotsize converters is reported. The switching time is sufficiently fast at 100 ps. Only 1 bit of the 10 Gbit/s signal is lost during switching. (6 Refs.) Classification: A4282 (Integrated optics); A4280L (Optical waveguides and couplers); A4280S (Optical communications devices); B4150 (Electro-optical devices); B4130 (Optical waveguides); B4140 (Integrated optics); B6260 (Optical links and equipment) Thesaurus: Aluminium compounds; Dynamic response; Electro-optical switches; Gallium arsenide; Gallium compounds; III-V semiconductors; Indium compounds; Integrated optics; Optical communication equipment; Optical directional couplers; Optical waveguides; Semiconductor quantum wells Free Terms: Dynamic response; Multiquantum well; MQW directional coupler; Waveguide switch modules; Packaged optical switch; Spotsize converters; 10 Gbit/s; 100 Ps; 1.55 Micron; InGaAlAs-InAlAs Numerical Index: Bit rate 1.0E+10 bit/s; Time 1.0E-10 s; Wavelength 1.55E-06 m Chemical Index: InGaAlAs-InAlAs/int InGaAlAs/int InAlAs/int Al/int As/int Ga/int In/int InGaAlAs/ss InAlAs/ss Al/ss As/ss Ga/ss In/ss Item Availability: CD-ROM. INSPEC 4823483 B9412-4320J-104 Doc Type: Conference Paper Title: Novel packaging technique for laser diode arrays using film carrier Authors: Usui, M.; Katsura, K.; Hayashi, T.; Hosoya, M.; Sato, K.; Sekine, S.; Toba, H. Affiliation: NTT Opto-Electron. Labs., Ibaraki, Japan Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 818-24 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0818$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: New development; Practical Abstract: An innovative packaging technique for laser diode (LD) arrays has been developed. This technique uses a new film carrier which has high-density inner leads and microstrip lines on polyimide film. There is less mutual inductance between lines on the film carrier than with the wiring structure we conventionally use which comprises bonding wire and Al/sub 2/O/sub 3/ circuit board. This structure can reduce the electrical crosstalk between channels on the LD array. A 4-channel LD array sub-module is fabricated employing the above technique, and demonstrated. The module has good frequency characteristics over a bandwidth of 2.3 GHz. The electrical crosstalk between adjacent LDs is less than -30 dB at 1 GHz. This value is about 10 dB lower than with the conventional wiring structure. (8 Refs.) Classification: B4320J (Semiconductor lasers); B0170J (Product packaging) Thesaurus: Crosstalk; Microstrip lines; Modules; Packaging; Polymer films; Semiconductor laser arrays Free Terms: Packaging; Laser diode arrays; Film carrier; Microstrip lines; Polyimide film; High-density inner leads; Mutual inductance; Electrical crosstalk; Four-channel sub-module; Fabrication; Frequency characteristics; Interconnection; 2.3 GHz; 1 GHz Numerical Index: Bandwidth 2.3E+09 Hz; Frequency 1.0E+09 Hz Item Availability: CD-ROM. INSPEC 4823448 B9412-2210D-090 Doc Type: Conference Paper Title: New metal board for COB, Multi-Chip Module, TAB and Phlip-Chip Authors: Okuno, A.; Oyama, N.; Hashimoto, T.; Kinoshita, H.; Shida, H. Affiliation: Japan Rec Co. Ltd., Osaka, Japan Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 555-9 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0555$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: New development; Practical; Experimental Abstract: Recently, the use of high-density mounting and multi-function design have been rapidly progressing on the industry. For metal board, the chip on board (COB) method has been widely employed with which a silicon chip is directly connected to a metal board by use of the wire bonding method. However, conventional metal boards are insufficient with respect to reliability. We have succeeded in the development of metal board having a high reliability by using a compound material high-purity, of a high-function naphthalene epoxy resin and an aramid paper from PPODTA (Co-poly-paraphenylene 3,4-oxydiphenylene terephthalamide) for its insulating layer which is the most important part with respect to reliability. The metal board is excellent in heat resistance and heat dissipation, and particularly in migration resistance. Its coefficient of linear expansion is 6 ppm board can be expected to be applied for advanced surface mounting technologies, such as LCCC, COB, Flip Chip, PGA, MCM (Multi Chip Module) and TAB. These applications are automobiles, air conditioners, air craft, space satellite, rocket and small-sized motors. (5 Refs.) Classification: B2210D (Printed circuit manufacture); B0170J (Product packaging); B2240 (Microassembly techniques); B0170N (Reliability); B2220J (Hybrid integrated circuits) Thesaurus: Circuit reliability; Flip-chip devices; Multichip modules; Printed circuit manufacture; Surface mount technology; Tape automated bonding Free Terms: Metal board; COB; Multi-Chip Module; TAB; Silicon chip; Wire bonding; Reliability; Naphthalene epoxy resin; Aramid paper; PPODTA; Co-poly-paraphenylene 3,4-oxydiphenylene terephthalamide; Insulating layer; Heat resistance; Heat dissipation; Migration resistance; Coefficient of linear expansion; Surface mounting technologies; LCCC; Flip Chip; PGA; High-density mounting; Multi-function design; Si Chemical Index: Si/int Si/el Item Availability: CD-ROM. INSPEC 4823379 B9412-1265F-052 C9412-5250-002 Doc Type: Conference Paper Title: A CPU chip-on-board module Authors: Yamada, K.; Tanaka, A.; Shinohara, H.; Honda, M.; Hatada, T.; Yamagiwa, A.; Shirai, Y. Affiliation: Res. Lab., Hitachi Ltd., Ibaraki, Japan Conf. Title: 1993 Proceedings. 43rd Electronic Components and Technology Conference (Cat. No.93CH3205-2) p. 8-11 Publisher: IEEE New York, NY, USA Date: 1993 xvii+1166 pp. Country of Publication: USA ISBN: 0 7803 0794 1 CCC: 0569-5503/93/0000-0008$3.00 Language: English Conf. Date: 1-4 June 1993 Conf. Loc: Orlando, FL, USA Treatment: Practical Abstract: A CPU chip-on-board module for low and mid-range computers is described. The module consists of a CPU bare chip, 24 SRAMs packaged in the SOJ and some bypass capacitors. The module substrate is a printed circuit board (PCB) made of imide-triazine resin. The module (156 mm*58 mm) consists of four signal metal layers and four power/ground metal layers. A square through hole (17 mm*17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded on the metal plate. The thermal resistance can be made smaller than 2 degrees C/W at a 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin grid array. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module. (8 Refs.) Classification: B1265F (Microprocessors and microcomputers); B0170J (Product packaging); B2210 (Printed circuits); C5250 (Microcomputer techniques) Thesaurus: Microcomputers; Modules; Printed circuits; Surface mount technology; Thermal resistance Free Terms: CPU COB module; Chip-on-board module; Computers; SRAMs; SOJ; PCB module substrate; Printed circuit board; Imide-triazine resin; Thermal spreading metal; Die-bonded chip; Thermal resistance; Electrical characteristics; Simultaneously switched noise; Microcomputer board Item Availability: CD-ROM. INSPEC 4765720 B9411-4320J-005 Doc Type: Journal Paper Title: A new packaging technique using a film carrier for laser diode arrays Authors: Usui, M.; Katsura, K.; Hayashi, T.; Hosoya, M.; Sato, K.; Sekine, S.; Toba, H. Affiliation: NTT Opto-Electron. Labs., Ibaraki, Japan Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 17 Iss: 3 p. 395-401 Date: Aug. 1994 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/94/$04.00 Language: English Treatment: New development; Experimental Abstract: This paper reviews a new packaging technique for laser diode (LD) arrays. This technique uses a new film carrier which has high-density inner leads and fanned-out microstrip line patterns on polyimide film. The film carrier is used to connect the LD array to peripheral circuits, such as LD drivers. There is less mutual inductance between lines on the film carrier than with the conventionally used airing structure which comprises bonding wire and an alumina (Al/sub 2/O/sub 3/) circuit board. This structure can reduce the electrical crosstalk between channels on the LD array with high-density interconnection. A 4-channel LD array sub-module is fabricated employing the above technique, and demonstrated. The module has good frequency characteristics over a bandwidth of 2.3 GHz. The electrical crosstalk between adjacent LDs is less than -30 dB at 1 GHz. This value is about 10 dB lower than with the conventional wiring structure. (9 Refs.) Classification: B4320J (Semiconductor lasers); B0170J (Product packaging); B4320M (Laser accessories and instrumentation) Thesaurus: Crosstalk; Laser accessories; Microstrip lines; Packaging; Polymer films; Semiconductor laser arrays Free Terms: Packaging; Film carrier; Laser diode arrays; Fanned-out microstrip line patterns; High-density inner leads; Polyimide film; Peripheral circuits; LD drivers; Mutual inductance; Electrical crosstalk; High-density interconnection; 4-Channel LD array sub-module; Frequency characteristics; 2.3 GHz; 1 GHz Numerical Index: Bandwidth 2.3E+09 Hz; Frequency 1.0E+09 Hz Item Availability: CD-ROM. INSPEC 4765712 B9411-1265F-003 C9411-5135-002 Doc Type: Journal Paper Title: 3D-WASP devices for on-line signal and data processing Authors: Hedge, S.J.; Habiger, C.M.; Lea, R.M. Affiliation: Aspex Microsystems Ltd., Brunel Univ., Uxbridge, UK Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 17 Iss: 3 p. 324-33 Date: Aug. 1994 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/94/$04.00 Language: English Treatment: Practical Abstract: While hybrid and monolithic Wafer-Scale Integration (WSI) technologies have brought about dramatic improvements in the density of integration of embedded massively parallel computers (MPCs), systems and applications engineers continue to demand ever more processing power in less space. The emerging technology of 3D-WSI offers a way of meeting this challenge, giving the potential for step-function increases in parallelism using existing WSI package options. It also permits independent scaling of I/O, parallel processing power and control, leading to a degree of cost-effectiveness that conventional 2D-WSI cannot match. The paper explores the potential of 3D-WASP (WSI Associative String Processor) and reports the results of a study into the engineering feasibility of such a device. This study suggests that a single 3D-WASP device, packages in a standard 2.5'*2.5'*0.25' can could deliver 100 Giga-OPS performance form 65536 processing elements, provide up to 64 input-output data channels of 16 bits each and dissipate only 25 W. (3 Refs.) Classification: B1265F (Microprocessors and microcomputers); C5135 (Digital signal processing chips); B2570 (Semiconductor integrated circuits); B6140 (Signal processing and detection); C5220P (Parallel architecture); C5260 (Digital signal processing); B0170J (Product packaging) Thesaurus: Digital signal processing chips; Packaging; Parallel architectures; VLSI Free Terms: 3D-WASP devices on-line signal processing on-line data processing massively parallel computers Wafer-Scale Integration 3D-WSI package WSI Associative String Processor 100 Giga-OPS input-output data channels; 16 Bit; 25 W; 2.5 In; 0.25 In Numerical Index: Word length 1.6E+01 bit; Power 2.5E+01 W; Size 6.4E-02 m; Size 6.3E-03 m Item Availability: CD-ROM. INSPEC 4756251 A9420-7560E-028 B9410-3110C-045 Doc Type: Conference Paper in Journal Title: Temperature dependence of the magnetization and of the other physical properties of rapidly quenched amorphous CoB alloys Authors: Konc, M.; Spisak, P.; Kollar, P.; Sovak, P.; Dusa, O.; Reininger, T. Affiliation: Dept. of Exp. Phys., Safarik (P.J.) Univ., Kosice, Slovakia Journal: IEEE Transactions on Magnetics Vol: 30 Iss: 2, pt.2 p. 524-6 Date: March 1994 Country of Publication: USA ISSN: 0018-9464 CODEN: IEMGAQ CCC: 0018-9464/94/$04.00 Language: English Conf. Title: 5th European Magnetic Materials and Applications Conference (EMMA '93) Conf. Date: 24-27 Aug. 1993 Conf. Loc: Kosice, Slovakia Conf. Sponsor: Comm. Eur. Communities; East Slovakian Ironworks, Kosice; Deutsche Phys. Gesellschaft E.V.; E.C.C.I.S., Kosice; City Council of Kosice; ISF, USA; MANICS, France; CRYOPHYSICS, S.A., Switzerland; EDIS, Slovakia Treatment: Experimental Abstract: We report here our results on magnetization study of amorphous Co/sub 100-x/B/sub x/ ribbons with 20<or=x<or=30 at.% B in the temperature range 10 K to 800 K and in applied magnetic field 5.10/sup 3/ A/m. The thermomagnetization curve is found to obey the Bloch law, M/sub s/(T)=M/sub s/(0)(1- beta T/sup 3/2/- gamma T/sup 5/2/, spin wave stiffness constant and the range of the exchange interaction were calculated from the experimental results. We have found that the B content has a strong effect on stiffness constant D. (10 Refs.) Classification: A7560E (Magnetization curves, hysteresis, Barkhausen and related effects); A7550K (Amorphous magnetic materials); A7550C (Ferromagnetism of other metals); A7530D (Spin waves in magnetically ordered materials); A7530E (Exchange and superexchange interactions in magnetically ordered materials); B3110C (Ferromagnetic materials) Thesaurus: Boron alloys; Cobalt alloys; Exchange interactions [electron]; Ferromagnetic properties of substances; Magnetic properties of amorphous substances; Magnetisation; Metallic glasses; Spin waves Free Terms: Magnetization; Temperature dependence; Physical properties; Rapidly quenched amorphous CoB alloys; Applied magnetic field; Thermomagnetization curve; Bloch law; Spin wave stiffness constant; Exchange interaction; 10 To 800 K; CoB Numerical Index: Temperature 1.0E+01 to 8.0E+02 K Chemical Index: CoB/bin Co/bin B/bin Item Availability: CD-ROM. INSPEC 4756236 A9420-7560E-023 B9410-3110C-041 Doc Type: Conference Paper in Journal Title: The Perminvar effect in binary amorphous CoB alloys Authors: Vojtanik, P.; Macko, D.; Lovas, A. Affiliation: Dept. of Exp. Phys., Safarik (P.J.) Univ., Kosice, Slovakia Journal: IEEE Transactions on Magnetics Vol: 30 Iss: 2, pt.2 p. 476-9 Date: March 1994 Country of Publication: USA ISSN: 0018-9464 CODEN: IEMGAQ CCC: 0018-9464/94/$04.00 Language: English Conf. Title: 5th European Magnetic Materials and Applications Conference (EMMA '93) Conf. Date: 24-27 Aug. 1993 Conf. Loc: Kosice, Slovakia Conf. Sponsor: Comm. Eur. Communities; East Slovakian Ironworks, Kosice; Deutsche Phys. Gesellschaft E.V.; E.C.C.I.S., Kosice; City Council of Kosice; ISF, USA; MANICS, France; CRYOPHYSICS, S.A., Switzerland; EDIS, Slovakia Treatment: Experimental Abstract: The time-temperature dependent Perminvar effect in amorphous Co/sub 100-x/B/sub x/ (x=17-30 at%) alloys was investigated in the temperature region of 150 to 450 K for stabilization times of up to 12 hours. After stabilization of the demagnetized domain structure the AC susceptibility (permeability) dependent on the driving magnetic field H shows a constant value up to the Perminvar critical field H/sub CR/. The fact that H/sub CR/ in CoB alloys can be higher than coercive field H/sub C/ is rather curious. In the Co/sub 75/B/sub 25/ alloy H/sub CR/ reaches values of 1.5 to 56 A/m dependent on the time and temperature of the stabilization. From the relative difference between two values of H/sub CR/ measured at two times t/sub 1/ and t/sub 2/ a magnetic relaxation spectrum similar to that obtained from reluctivity have been constructed. The kinetics of the H/sub CR/ increase measured at different temperatures indicates that relaxation parameters are equal to those obtained from the magnetic reluctivity aftereffect and that both effects have the same inherent nature. (6 Refs.) Classification: A7560E (Magnetization curves, hysteresis, Barkhausen and related effects); A7560C (Magnetic domain walls and domain structure); A7560L (Magnetic aftereffects); A7530C (Magnetic moments and susceptibility in magnetically ordered materials); A7550K (Amorphous magnetic materials); B3110C (Ferromagnetic materials) Thesaurus: Boron alloys; Cobalt alloys; Coercive force; Ferromagnetic properties of substances; Magnetic aftereffect; Magnetic domains; Magnetic permeability; Magnetic properties of amorphous substances; Magnetic relaxation; Magnetic susceptibility Free Terms: Perminvar effect; Binary amorphous CoB alloys; Stabilization times; Demagnetized domain structure; AC susceptibility; Permeability; Driving magnetic field; Perminvar critical field; Coercive field; Magnetic relaxation spectrum; Magnetic reluctivity aftereffect; 150 To 450 K; Co/sub 75/B/sub 25/; CoB Numerical Index: Temperature 1.5E+02 to 4.5E+02 K Chemical Index: Co75B25/bin Co75/bin B25/bin Co/bin B/bin; CoB/bin Co/bin B/bin Item Availability: CD-ROM. INSPEC 4720883 B9409-0170J-012 Doc Type: Conference Paper Title: Thermomechanical reliability assessment in SM- and COB-technology by combined experimental and finite element method Authors: Dudek, R.; Michel, B. Affiliation: Fraunhofer Inst. for Reliability & Microintegration, Berlin, Germany Conf. Title: 1994 IEEE International Reliability Physics Proceeding. 32nd Annual (Cat. No.94CH3332-4) p. 458-65 Publisher: IEEE New York, NY, USA Date: 1994 xi+505 pp. Country of Publication: USA ISBN: 0 7803 1357 7 CCC: CH3332-4/94/0000-0458$01.00 Language: English Conf. Date: 11-14 April 1994 Conf. Loc: San Jose, CA, USA Conf. Sponsor: IEEE Electron Devices Soc.; IEEE Reliability Soc Treatment: Theoretical/Mathematical; Experimental Abstract: In the paper, the authors address the issue of thermo-mechanically stressed microelectronic assemblies. An approach combining finite element simulation and advanced in-situ measuring techniques are presented. Examples given in the text illustrate the application of the experimental methods such as micro moire technique, speckle pattern photography or X-ray stress analysis in connection with numerical simulations. Finally, actual results concerning solder joint reliability are discussed. (7 Refs.) Classification: B0170J (Product packaging); B0170N (Reliability); B2210 (Printed circuits); B0290T (Finite element analysis) Thesaurus: Circuit reliability; Finite element analysis; Moire fringes; Photographic applications; Soldering; Surface mount technology; X-ray analysis Free Terms: Thermomechanical reliability assessment; COB-technology; Finite element method; Microelectronic assemblies; In-situ measuring techniques; Micro moire technique; Speckle pattern photography; X-ray stress analysis; Solder joint reliability; SM-technology Item Availability: CD-ROM. INSPEC 4710853 B9408-0120-040 Doc Type: Conference Paper Title: A Dutch-US microelectronic collaboration Authors: van Slooten, J.; Witteveen, F.J.F.M.; de Gruijter, R.; Gunnewiek, R.K.; Bijker, H.J.; Pearson, R.E.; Fuller, L.F. Affiliation: Dept. of Electron., Hogesch. Enschede, Netherlands Conf. Title: Proceedings of the Tenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.93CH3273-0) p. 166-9 Publisher: IEEE New York, NY, USA Date: 1993 x+253 pp. Country of Publication: USA ISBN: 0 7803 0990 1 CCC: 0 7803 0990 1/93/$03.00 Language: English Conf. Date: 18-19 May 1993 Conf. Loc: Research Triangle Park, NC, USA Conf. Sponsor: IEEE; SRC; SEMATECH; North Carolina State Univ Treatment: General/Review Abstract: The interaction between a European educational institution, i.e., the Electrical Engineering Department of the Hogeschool Enschede (HE), in the Netherlands and the Microelectronic Engineering Department of the Rochester Institute of Technology (RIT) in the US is described. Six students from the Netherlands have come to the US to complete a thesis for graduation from Hogeschool Enschede. One student conducted a six-month project on the design, simulation, fabrication, and testing of CMOS circuits. These institutions are described, together with the student's project. (5 Refs.) Classification: B0120 (Education and training); B2570D (CMOS integrated circuits); B0170C (Project and design engineering) Thesaurus: CMOS integrated circuits; Education; Integrated circuit technology; Project engineering Free Terms: Boundary scan circuit design; Education; QuickSim simulation; Dutch-US microelectronic collaboration; Simulation; Fabrication; Testing; CMOS circuits Item Availability: CD-ROM. INSPEC 4710824 B9408-0120-030 Doc Type: Conference Paper Title: Microelectronic engineering at RIT-10 years of industry partnership Authors: Fuller, L.F.; Pearson, R.E.; Turkman, I.R.; Kurinec, S.; Lane, R.L.; Jackson, M.A.; Smith, B.W. Affiliation: Microelectron. Eng., Rochester Inst. of Technol., NY, USA Conf. Title: Proceedings of the Tenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.93CH3273-0) p. 23-8 Publisher: IEEE New York, NY, USA Date: 1993 x+253 pp. Country of Publication: USA ISBN: 0 7803 0990 1 CCC: 0 7803 0990 1/93/$03.00 Language: English Conf. Date: 18-19 May 1993 Conf. Loc: Research Triangle Park, NC, USA Conf. Sponsor: IEEE; SRC; SEMATECH; North Carolina State Univ Treatment: General/Review Abstract: The microelectronic engineering program at Rochester Institute of Technology (RIT) is the only ABET accredited B.S. Microelectronic Engineering program in the United States. The program requires co-op, making it five years in length. Co-op students alternate six months of co-op employment with six months of school. Currently 250 students are in the program and more than 300 graduates are employed (mostly as process engineers) at semiconductor manufacturing locations nationwide. The undergraduate and graduate curricula are discussed. A description of the laboratory facility is included. (10 Refs.) Classification: B0120 (Education and training); B2570 (Semiconductor integrated circuits) Thesaurus: Educational courses; Integrated circuits Free Terms: Undergraduate curriculum; Microelectronic engineering program; Semiconductor manufacturing; Graduate curricula; Laboratory facility Item Availability: CD-ROM. INSPEC 4707132 B9408-0170J-051 Doc Type: Journal Paper Title: Printing encapsulation systems (PES) of advanced multichip module and COB device Authors: Okuno, A.; Nagai, K.; Oyama, N.; Hashimoto, T.; Onishi, T.; Wakamoto, S.; Masui, K. Affiliation: Japan Rec. Co. Ltd., Osaka, Japan Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 17 Iss: 1 p. 119-23 Date: Feb. 1994 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/94/$04.00 Language: English Treatment: Application; Practical Abstract: Extensive study of methods to screen print an encapsulant on bare die for multichip modules (MCM) and chip-on-board (COB), TAB, and flip-chip applications has produced a 'printing encapsulation system' (PES). The key to this system was in the development of a liquid epoxy resin with optimum properties for printing encapsulation. We have developed a printing encapsulation system (PES) that produces high reliability and high quality encapsulated components, free of voids and demonstrating optimal thin consistent encapsulated shapes for advanced COB applications. The PES utilizes an epoxy resin we created with viscosity and open lid storage properties appropriate for mass production. The thixotropic properties have been adjusted carefully to allow for consistent high volume results. The system yields a void free encapsulated device that a is resistant to thermal shock and moisture after short cure times. Full curing can be achieved in as short as 15 min, lending this material and process easily to in-line manufacturing. (5 Refs.) Classification: B0170J (Product packaging); B0170N (Reliability); B2220J (Hybrid integrated circuits) Thesaurus: Circuit reliability; Encapsulation; Flip-chip devices; Multichip modules; Tape automated bonding Free Terms: Advanced multichip module; COB device; Printing encapsulation systems; Bare die; TAB; Flip-chip applications; Liquid epoxy resin; Reliability; Optimal thin consistent encapsulated shapes; Viscosity; Open lid storage properties; Thixotropic properties; Void free encapsulated device; Cure times; In-line manufacturing Item Availability: CD-ROM. INSPEC 4707131 B9408-0170J-050 C9408-5490-005 Doc Type: Journal Paper Title: A CPU chip-on-board module Authors: Tanaka, A.; Shinohara, H.; Yamada, K.; Honda, M.; Hatada, T.; Yamagiwa, A.; Shirai, Y. Affiliation: Res. Lab., Hitachi Ltd., Ibaraki, Japan Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 17 Iss: 1 p. 115-18 Date: Feb. 1994 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/94/$04.00 Language: English Treatment: Practical Abstract: A CPU chip-on-board module for low and midrange computers is described. The module consists of a CPU bare chip, 24 SRAM's packaged in SOJ packages, and some decoupling capacitors. The module substrate is a printed circuit board (PCB) made of bismaleimide-triazine resin. The module (156 mm*58 mm) consists of four signal metal layers and four power/ground metal layers. A square clearance hole (17 mm*17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded onto the metal plate. The thermal resistance can be made smaller than 2 degrees C/W with 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin-grid array package. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module. (8 Refs.) Classification: B0170J (Product packaging); B1265F (Microprocessors and microcomputers); C5490 (Other aspects of analogue and digital computers); C5130 (Microprocessor chips) Thesaurus: Microprocessor chips; Modules; Packaging; Thermal resistance Free Terms: CPU chip-on-board module; Decoupling capacitors; CPU bare chip; SRAMs; SOJ packages; Bismaleimide-triazine resin PCB; Signal metal layers; Power/ground metal layers; Square clearance hole; Thermal spreading metal; Thermal resistance; Electrical characteristics; Signal delay time; Cache memories; Simultaneously switched noise Item Availability: CD-ROM. INSPEC 4705967 B9408-0170J-027 Doc Type: Conference Paper Title: Development of the RIT infrastructure for design, fabrication and testing of small multichip modules Authors: Mukund, P.R.; Pearson, R.E. Affiliation: Rochester Inst. of Technol., NY, USA Conf. Title: Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93 (Cat. No.93CH3224-3) p. 58-60 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1993 xi+203 pp. Country of Publication: USA ISBN: 0 8186 3540 1 CCC: 0 8186 3540 1/93/$3.00 Language: English Conf. Date: 15-18 March 1993 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: The infrastructural work in progress at the Rochester Institute of Technology in the area of the multichip modules is described. Facilities for design, fabrication and testing are being developed. Present capabilities as well as future goals are presented. The MCM effort is a joint effort between the Electrical Engineering department and the Microelectronic department. Issues related to design, simulation (electrical and thermal) and testing are being addressed in the Electrical Engineering department. Mask making, fabrication, and final packaging are being handled by the Microelectronic Engineering department. The facilities, technology and projects (ongoing and future) in this endeavor are considered. (1 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits); B0170C (Project and design engineering) Thesaurus: Design engineering; Integrated circuit technology; Integrated circuit testing; Masks; Multichip modules; Project management Free Terms: Multichip module design; MCM fabrication; MCM testing; Mask fabrication; Thermal simulation; Electrical simulation; RIT infrastructure; Packaging Item Availability: CD-ROM. INSPEC 4677698 B9407-0170J-018 Doc Type: Conference Paper Title: Advanced TAB/BGA multi-chip stacked module for high density LSI packages Authors: Mita, M.; Kumakura, T.; Inoue, S.; Hiraki, Y. Affiliation: Dept. of Electron. Mater. Eng., Hitachi Cable Ltd., Densen, Japan Conf. Title: Proceedings 1994 IEEE Multi-Chip Module Conference MCMC-94 (Cat. No.93CH3396-9) p. 68-76 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 xi+149 pp. Country of Publication: USA ISBN: 0 8186 5560 7 CCC: 0 8186 5560 7/94/$03.00 Language: English Conf. Date: 15-17 March 1994 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: New development; Practical Abstract: A newly advanced design for a TAB/BGA multi-chip stacked module has been developed for high density LSI packages. The configuration of this module is designed to reduce package body size and to lighten the weight. Electrical and thermal performance of this module was carefully considered and estimated by simulation or experiments. This module is called a COCB module which means the Chip On Chip Ball Grid Array module. Two chips are mounted on both top and bottom sides of a small substrate by TAB technology using a new Au-Sn (Au10-40%-Sn) eutectic micro-connection method. Two chips are electrically connected by routing wires and through holes of an interposed substrate respectively. This module is useful when packages are mounted on a board with solder paste, directly to its surface, with some discrete packages on the assembly line. The authors propose the concept of the micro bare chip module. (8 Refs.) Classification: B0170J (Product packaging); B2240 (Microassembly techniques); B2570 (Semiconductor integrated circuits); B0170N (Reliability) Thesaurus: Circuit reliability; Large scale integration; Microassembling; Multichip modules; S-parameters; Tape automated bonding Free Terms: TAB/BGA multi-chip stacked module; High density LSI packages; Electrical performance; Thermal performance; Simulation; COCB module; Chip on chip ball grid array module; TAB technology; Au-Sn eutectic microconnection method; Solder paste mounting; Micro bare chip module; LSI chip interconnection; S-parameters; Crosstalk; Thermal dissipation; Reliability test; Fine pitch interconnection; AuSn Chemical Index: AuSn/int Au/int Sn/int AuSn/bin Au/bin Sn/bin Item Availability: CD-ROM. INSPEC 4677696 B9407-0170J-016 Doc Type: Conference Paper Title: Laminated memory: a new 3-dimensional packaging technology for MCMs Authors: Tuckerman, D.B.; Bauer, L.-O.; Brathwaite, N.E.; Demmin, J.; Flatow, K.; Hsu, R.; Kim, P.; Lin, C.-M.; Lin, K.; Nguyen, S.; Thipphavong, V. Affiliation: nChip Inc., San Hose, CA, USA Conf. Title: Proceedings 1994 IEEE Multi-Chip Module Conference MCMC-94 (Cat. No.93CH3396-9) p. 58-63 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 xi+149 pp. Country of Publication: USA ISBN: 0 8186 5560 7 CCC: 0 8186 5560 7/94/$03.00 Language: English Conf. Date: 15-17 March 1994 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: New development; Practical Abstract: A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate ('MCM-D'), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests. (17 Refs.) Classification: B0170J (Product packaging); B1265D (Memory circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Economics; Integrated circuit manufacture; Integrated memory circuits; Multichip modules; VLSI Free Terms: Laminated memory; 3D packaging technology; MCMs; Multichip module substrate; Memory chip stacking; High-performance thin-film interconnection substrate; MCM-D; Substrate cost; Memory-intensive design; Assembly cost; MCM cost; High wiring density; Substrate thermal conductivity; Dicing; Adhesive die attach; Wire bonding equipment; Functional memory modules; Thermal shock tests Item Availability: CD-ROM. INSPEC 4673310 B9406-1265F-076 C9406-5135-023 Doc Type: Conference Paper Title: 3D-WASP devices for on-line signal and data processing Authors: Hedge, S.J.; Habiger, C.M.; Lea, R.M. Affiliation: Aspex Microsyst., Brunel Univ., Uxbridge, UK Conf. Title: 1994 Proceedings. Sixth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.94CH3412-4) p. 11-21 Editors: Lea, R.M.; Tewksbury, S. Publisher: IEEE New York, NY, USA Date: 1994 ix+404 pp. Country of Publication: USA ISBN: 0 7803 1850 1 CCC: 0 7803 1850 1/94/$3.00 Language: English Conf. Date: 19-21 Jan. 1994 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Application; Practical Abstract: While hybrid and monolithic-WSI technologies have brought about dramatic improvements in the density of integration of embedded massively parallel computers (MPCs), systems and applications engineers continue to demand even more processing power in less space. The emerging technology of 3D-WSI offers a way of meeting this challenge, giving the potential for step-function increases in parallelism using existing WSI package options. It also permits independent scaling of I/O, parallel processing power and control, leading to a degree of cost-effectiveness that 2D-WSI cannot match. The paper explores the potential of 3D-WASP and reports the results of a study into the engineering feasibility of such a device. (3 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); C5135 (Digital signal processing chips); C5220P (Parallel architecture) Thesaurus: Digital signal processing chips; Parallel architectures; VLSI Free Terms: 3D-WASP devices; Parallelism; WSI package options; Parallel processing; Cost-effectiveness; Engineering feasibility; Embedded massively parallel computers; WSI associative string processors Item Availability: CD-ROM. INSPEC 4638144 A9410-4282-005 B9405-4140-018 Doc Type: Journal Paper Title: 2*2 InGaAlAs/InAlAs multiquantum well (MQW) directional coupler waveguide switch modules integrated with spotsize convertors Authors: Kawano, K.; Kohtoku, M.; Yoshimoto, N.; Sekine, S.; Noguchi, Y. Affiliation: Opto-Electron. Lab., NTT Corp., Kanagawa, Japan Journal: Electronics Letters Vol: 30 Iss: 4 p. 353-5 Date: 17 Feb. 1994 Country of Publication: UK ISSN: 0013-5194 CODEN: ELLEAK CCC: 0013-5194/94/$7.50+0.00 Language: English Treatment: Practical Abstract: The authors report the first ever fully packaged practical 2*2 InGaAlAs/InAlAs MQW waveguide switch modules integrated with newly proposed efficient spotsize convertors. The connector-to-connector insertion loss and crosstalk of switch modules are 16 and -15 dB, respectively. The spotsize conversion loss, including coupling loss to arrayed polarisation-maintaining (PANDA) singlemode fibres (SMFs) is, on average. 2.3 dB per port. (8 Refs.) Classification: A4282 (Integrated optics); A4280L (Optical waveguides and couplers); A4280S (Optical communications devices); B4140 (Integrated optics); B4270 (Integrated optoelectronics); B4130 (Optical waveguides); B0170J (Product packaging); B6260 (Optical links and equipment) Thesaurus: Aluminium compounds; Directional couplers; Gallium arsenide; Gallium compounds; III-V semiconductors; Indium compounds; Integrated optics; Integrated optoelectronics; Losses; Modules; Optical communication equipment; Optical couplers; Optical switches; Packaging; Semiconductor quantum wells; Semiconductor switches Free Terms: InGaAlAs/InAlAs; Multiquantum well; Directional coupler; MQW waveguide switch modules; Spotsize convertors; Connector-to-connector insertion loss; Crosstalk; Conversion loss; Coupling loss; Arrayed polarisation-maintaining fibres; PANDA; Singlemode fibres; 2.3 DB; InGaAlAs-InAlAs Numerical Index: Loss 2.3E+00 dB Chemical Index: InGaAlAs-InAlAs/int InGaAlAs/int InAlAs/int Al/int As/int Ga/int In/int InGaAlAs/ss InAlAs/ss Al/ss As/ss Ga/ss In/ss Item Availability: CD-ROM. INSPEC 4561763 A9403-4260F-036 B9402-4320J-077 Doc Type: Journal Paper Title: Simultaneous operation of ten-channel tunable DFB laser arrays using strained-InGaAsP multiple quantum wells Authors: Sato, K.; Sekine, S.; Kondo, Y.; Yamamoto, M. Affiliation: Opto-Electronics Lab., NTT, Kanagawa, Japan Journal: IEEE Journal of Quantum Electronics Vol: 29 Iss: 6 p. 1805-9 Date: June 1993 Country of Publication: USA ISSN: 0018-9197 CODEN: IEJQA7 CCC: 0018-9197/93/$03.00 Language: English Treatment: Experimental Abstract: Simultaneous operation of a ten-channel tunable multisection lambda /4-shifted distributed-feedback (DFB) laser array using strained-InGaAsP multiple quantum wells is described. The lasing frequencies of the ten channels are all set in a single 10-GHz space, with each channel maintaining a narrow linewidth of less than 2.3 MHz. This array has potential applications for optical frequency-division-multiplexing systems. (23 Refs.) Classification: A4260F (Laser beam modulation, pulsing and switching; mode locking and tuning); A4260B (Design of specific laser systems); A4255P (Lasing action in semiconductors); B4320J (Semiconductor lasers) Thesaurus: Distributed feedback lasers; Gallium arsenide; Gallium compounds; III-V semiconductors; Indium compounds; Laser tuning; Semiconductor laser arrays; Semiconductor lasers Free Terms: Ten channel tunable multisection quarter wavelength shifted; Distributed feedback laser array; Simultaneous operation; Strained-InGaAsP multiple quantum wells; Lasing frequencies; Linewidth; Optical frequency-division-multiplexing systems; InGaAsP Chemical Index: InGaAsP/int As/int Ga/int In/int P/int InGaAsP/ss As/ss Ga/ss In/ss P/ss Item Availability: CD-ROM. INSPEC 4503600 B9311-0170J-019 Doc Type: Conference Paper Title: Active silicon substrate technology for miniaturized ultra high performance processing Authors: Malek, H.; Pearson, R. Affiliation: Lockheed Missiles & Space Co. Inc., Palo Alto, CA, USA Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 346-57 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A multichip module (MCM) technology called active silicon substrate (ASIS) that raises architectural design of signal/data processing systems to much higher levels of microminiaturization and performance is described. The merits of active substrates over the conventional passive ones are demonstrated through the implementation of several features that are possible when active elements are embedded in the interconnecting substrate and mounting platform. These include scalable fault-tolerant computing elements, replaceable drivers/buffers, and embedded local/global self-test circuits. The ASIS technology allows more than one type of processing architecture to be embedded and integrated in the same substrate, thus providing a viable approach for water scale integration. (7 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Digital integrated circuits; Hybrid integrated circuits; Integrated circuit technology; Multichip modules; Silicon; Substrates; VLSI Free Terms: WSI; Packaging; Miniaturized ultra high performance processing; Multichip module; MCM; Interconnecting substrate; Mounting platform; Scalable fault-tolerant computing elements; Replaceable drivers/buffers; Embedded local/global self-test circuits; ASIS technology; Processing architecture; Water scale integration; Active Si substrate technology Chemical Index: Si/sur Si/el Item Availability: CD-ROM. INSPEC 4503587 B9311-1265F-060 C9311-5130-037 Doc Type: Conference Paper Title: Interface design optimisation for WASP devices Authors: Bolouri, H.; Hussaini, M.B.A.; Hedge, S.J.; Lea, R.M. Affiliation: Hertfordshire Univ., Hatfield, UK Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 223-32 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: Details of defect and fault tolerance strategies used in the wafer interface blocks of wafer scale integration (WSI) associative string processor (WASP) devices are given. A structured approach to the design and optimization of redundant-path defect- and fault-tolerant signal distribution networks is presented. Monte Carlo simulations are used to analyze the success rate of various WASP signal distribution network topologies in the presence of randomly distributed defects. It is shown that the proposed signal distribution strategy lends itself well to high-speed recovery from in-operation failures. (5 Refs.) Classification: B1265F (Microprocessors and microcomputers); B0240G (Monte Carlo methods); C5130 (Microprocessor chips); C5470 (Performance evaluation and testing); C5220P (Parallel architecture); C1140G (Monte Carlo methods) Thesaurus: Fault tolerant computing; Microprocessor chips; Monte Carlo methods; Network topology; Parallel architectures; VLSI Free Terms: Redundant-path defect-networks; WASP devices; Fault tolerance strategies; Wafer interface blocks; Wafer scale integration; Associative string processor; Fault-tolerant signal distribution networks; Monte Carlo simulations; Signal distribution network topologies; High-speed recovery Item Availability: CD-ROM. INSPEC 4503566 B9311-1265F-050 C9311-5130-033 Doc Type: Conference Paper Title: The development of the WASP 3 processor Authors: Jalowiecki, I.P.; Hedge, S.J.; Williams, R. Affiliation: Brunel Univ., Uxbridge, UK Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 20-9 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Application; Practical Abstract: The ASP (associative string processor) is a massively parallel, fault tolerant, fully associative processor designed for the implementation of very compact, easily extensible, modular low-multiple-instruction, multiple-data/high-single-instruction multiple-data (low-MIMD/high-SIMD) parallel processing systems. It is capable of supporting real-world applications of continuous data input and tightly integrated numeric and symbolic computations. The ASP module architecture and the wafer-scale (WASP-3) concept are described. (6 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); C5130 (Microprocessor chips); C5220P (Parallel architecture) Thesaurus: Microprocessor chips; Parallel architectures; VLSI Free Terms: Wafer-scale associative string processor; Massively parallel processor; Numeric computations; Fault tolerance; Low-MIMD/high-SIMD parallel processing; Modular low-multiple-instruction; Multiple-data; High-single-instruction multiple-data; Continuous data input; Symbolic computations; ASP module architecture Item Availability: CD-ROM. INSPEC 4479735 A9320-4260B-012 B9310-4320J-036 Doc Type: Journal Paper Title: Thermal interaction in a distributed-feedback laser diode (DFB LD) array module Authors: Hayashi, T.; Sato, K.; Sekine, S. Affiliation: NTT Interdisciplinary Res. Lab., Tokyo, Japan Journal: Journal of Lightwave Technology Vol: 11 Iss: 3 p. 442-7 Date: March 1993 Country of Publication: USA ISSN: 0733-8724 CODEN: JLTEDG CCC: 0733-8724/93/$03.00 Language: English Treatment: Practical; Experimental Abstract: The thermal interaction in a four-element distributed-feedback laser diode (LD) array module is investigated. When the injection current of each element was 200 mA, the interactive temperature rise of an element at one end was 6.6 degrees C. At the same time, temperature rise of the mounting structure (submount, header, and heatsink) was 4.9 degrees C, or about 75% of the interactive temperature rise of the element. According to two-dimensional thermal analysis, the temperature rise of the mounting structure accounts for 98% of the interactive temperature rise of the element. These experimental and analytical results show that the temperature rise in the mounting structure is the main cause of the interactive temperature rise of this module. Stabilization of the submount temperature instead of the heatsink temperature reduced the interactive temperature rise due to the three neighboring elements to 1/3 of that achieved by conventional heatsink temperature stabilization. The thermal analysis also showed that a thicker submount further reduces the thermal interaction in an LD array module. (14 Refs.) Classification: A4260B (Design of specific laser systems); A4255P (Lasing action in semiconductors); B4320J (Semiconductor lasers); B0170J (Product packaging) Thesaurus: Distributed feedback lasers; Modules; Packaging; Semiconductor laser arrays; Temperature distribution; Thermal analysis Free Terms: DFB LD array module; Thermal interaction; Distributed-feedback laser diode; Injection current; Temperature rise; Mounting structure; Two-dimensional thermal analysis; 200 MA Numerical Index: Current 2.0E-01 A Item Availability: CD-ROM. INSPEC 4432494 B9308-2220J-004 Doc Type: Conference Paper Title: Effect of molding compound thermal conductivity on thermal performance of molded multi-chip modules Authors: Azar, K.; Mandrone, C.D.; Segelken, J.M. Affiliation: AT&T Bell Lab., Andover, MA, USA Conf. Title: Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.93CH3226-8) p. 19-27 Publisher: IEEE New York, NY, USA Date: 1993 x+214 pp. Country of Publication: USA ISBN: 0 7803 0863 8 CCC: 0 7803 0863 8/93/$3.00 Language: English Conf. Date: 2-4 Feb. 1993 Conf. Loc: Austin, TX, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: Exploratory work has been carried out to investigate filled epoxy systems for thermal management enhancements for plastic encapsulated integrated circuits. A computational study was conducted to examine the effect of molding compound thermal conductivity on thermal resistance of a molded multi-chip module. Seven different molding thermal conductivities were considered. The air velocity was varied from natural convection to high-velocity forced convection. The results showed that an eight-fold increase in molding compound thermal conductivity reduces the junction-to-ambient thermal resistance by 20% in natural convection and by 54% in high-velocity forced convection. (9 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging) Thesaurus: Convection; Cooling; Multichip modules Free Terms: Molding compound thermal conductivity; Thermal performance; Molded multi-chip modules; Filled epoxy systems; Thermal management enhancements; Plastic encapsulated integrated circuits; Air velocity; Natural convection; High-velocity forced convection; Thermal conductivity; Junction-to-ambient thermal resistance Item Availability: CD-ROM. INSPEC 4424511 B9307-8110-020 C9307-7410B-112 Doc Type: Journal Paper Title: Three phase harmonic modelling of power system loads Authors: Palmer, E.W.; Ledwich, G.F. Affiliation: Sch. of Electr. & Electron. Syst., Queensland Univ. of Technol., Brisbane, Qld, Australia Journal: IEE Proceedings C [Generation, Transmission and Distribution] Vol: 140 Iss: 3 p. 206-12 Date: May 1993 Country of Publication: UK ISSN: 0143-7046 CODEN: IPPDDA CCC: 0143-7046/93/$7.50+0.00 Language: English Treatment: Theoretical/Mathematical Abstract: This paper reports the development and testing of a method for modelling distribution load impedances as unbalanced three phase impedance matrices for detailed harmonic studies. The experimental testing of this method was performed using data obtained from capacitor switching and transformer tap changing disturbances. This method is applicable even in situations where harmonic sources within the load exist provided that the output of these sources is effectively uncorrelated with the applied disturbance. Computer simulation results gave a measure of the self impedances, accurate to within 5% at the resonant peaks, but gave a considerably less accurate measure of the mutuals. The results obtained from measurements taken at the supply end of a distribution feeder show that the disturbance resulting from a transformer tap change event can give results consistent with those obtained from the much larger capacitor switching disturbance. (12 Refs.) Classification: B8110 (Power systems); B0210 (Algebra); B8350 (Transformers and reactors); B8390 (Other power apparatus and electric machines); C7410B (Power engineering computing) Thesaurus: Distribution networks; Load [electric]; Matrix algebra; Power capacitors; Power system analysis computing; Power system harmonics; Power transformers; Switching Free Terms: Power system harmonics; Power system analysis computing; Digital simulation; Modelling; Loads; Unbalanced three phase impedance matrices; Capacitor switching; Transformer tap changing disturbances; Self impedances; Distribution feeder Item Availability: CD-ROM. INSPEC 4409588 B9307-2810D-004 Doc Type: Journal Paper Title: Studies on the improvement of breakdown strength of polyolefins Authors: Niwa, T.; Hatada, M.; Miyata, H.; Takahashi, T. Affiliation: Fujikura Ltd., Tokyo, Japan Journal: IEEE Transactions on Electrical Insulation Vol: 28 Iss: 1 p. 30-4 Date: Feb. 1993 Country of Publication: USA ISSN: 0018-9367 CODEN: IETIAX CCC: 0018-9367/93/$3.00 Language: English Treatment: Experimental Abstract: Breakdown tests were conducted on a variety of polyethylenes and polypropylenes. High density polyethylene (HDPE) and polypropylene random copolymers (PPR) exhibited the highest breakdown strengths among the examined polyolefins. Model cables insulated with HDPE and PPR were manufactured, and the impulse breakdown strength of the HDPE cables made under some specific manufacturing conditions was 1.6*larger than that of conventional crosslinked polyethylene (XLPE). However, improvements were not observed in the impulse breakdown strength of PPR. The AC breakdown strength of HDPE and PPR cables also did not improve. The reason for the improvement in impulse breakdown strength of HDPE is the increased crystallinity of the insulating material, is brought about by the heat annealing applied to the cable in a manufacturing process. (5 Refs.) Classification: B2810D (Dielectric breakdown and discharges); B8130B (Power cables); B2830C (Organic insulation) Thesaurus: Annealing; Cable insulation; Electric breakdown of solids; Electric strength; Impulse testing; Insulation testing; Organic insulating materials; Polymer blends; Polymers Free Terms: High density polyethylene; Breakdown test; Model cable; Polypropylene random copolymers; Polyolefins; PPR; Impulse breakdown strength; HDPE cables; Manufacturing conditions; Crosslinked polyethylene; XLPE; AC breakdown strength; PPR cables; Crystallinity; Insulating material; Heat annealing; Manufacturing process Item Availability: CD-ROM. INSPEC 4392509 B9306-4250-005 Doc Type: Journal Paper Title: Silicon carbide UV photodiodes Authors: Brown, D.M.; Downey, E.T.; Ghezzo, M.; Kretchmer, J.W.; Saia, R.J.; Liu, Y.S.; Edmond, J.A.; Gati, G.; Pimbley, J.M.; Schneider, W.E. Affiliation: General Electric Co., Schenectady, NY, USA Journal: IEEE Transactions on Electron Devices Vol: 40 Iss: 2 p. 325-33 Date: Feb. 1993 Country of Publication: USA ISSN: 0018-9383 CODEN: IETDAI CCC: 0018-9383/93/$03.00 Language: English Treatment: Practical; Experimental Abstract: SiC photodiodes were fabricated using 6 H single-crystal wafers. These devices have excellent UV responsivity characteristics and very low dark current even at elevated temperatures. The reproducibility is excellent and the characteristics agree with theoretical calculations for different device designs. The advantages of these diodes are that they will operate at high temperatures and are responsive between 200 and 400 nm and not responsive to longer wavelengths because of the wide 3-eV bandgap. The responsivity at 270 nm is between 70% and 85%. Dark-current levels have been measured as a function of temperature that are orders of magnitude below those previously reported. Thus, these diodes can be expected to have excellent performance characteristics for detection of low light level UV even at elevated temperatures. (9 Refs.) Classification: B4250 (Photoelectric devices); B7230C (Photodetectors) Thesaurus: Leakage currents; Photodiodes; Semiconductor materials; Short-circuit currents; Silicon compounds; Ultraviolet detectors Free Terms: Low light level UV detection; Reverse current leakage; Short circuit output current; Quantum efficiency; 6H epitaxial layers; UV responsivity characteristics; Low dark current; Reproducibility; 200 To 400 nm; SiC photodiodes Numerical Index: Wavelength 2.0E-07 to 4.0E-07 m Chemical Index: SiC/int Si/int C/int SiC/bin Si/bin C/bin Item Availability: CD-ROM. INSPEC 4382411 B9305-5270B-038 Doc Type: Conference Paper Title: The radiation characteristic of a lambda /4-monopole antenna mounted on a conducting body with a notch (portable telephone model) Authors: Sekine, S.; Maeda, T. Affiliation: Toshiba Corp., Kawasaki, Japan Conf. Title: IEEE Antennas and Propagation Society International Symposium. 1992 Digest. Held in Conjuction with: URSI Radio Science Meeting and Nuclear EMP Meeting (Cat. No.92CH3178-1) p. 65-8 vol.1 Publisher: IEEE New York, NY, USA Date: 1992 4 vol. xii+2324 pp. Country of Publication: USA ISBN: 0 7803 0730 5 CCC: 0 7803 0730 5/92$03.00 Language: English Conf. Date: 18-25 July 1992 Conf. Loc: Chicago, IL, USA Conf. Sponsor: IEEE; Motorola; Andrew Corp.; Cray Res.; Illinois Inst. Technol.; Northwestern Univ.; Univ. Illinois Treatment: Theoretical/Mathematical Abstract: The authors describe the radiation characteristic and the current distributions of a lambda /4-monopole antenna on the conducting body modeled as an ordinary portable telephone by simulation using the time domain method. The results show that the current on the conducting body has an undesirable influence on the radiation of the antenna. A novel method is proposed to prevent such an undesirable influence by cutting a notch in the conducting body. In terms of the radiation characteristic of the model with such a notch, the results of simulation and an experiment agree and indicate good performance. (4 Refs.) Classification: B5270B (Single antennas); B5260 (Antenna theory); B6250F (Mobile radio systems); B6220C (Telephone stations) Thesaurus: Antenna radiation patterns; Current distribution; Mobile antennas; Monopole antennas; Radiotelephony; Telephone sets; Time-domain analysis Free Terms: Notched conducting body; Radiation characteristic; Lambda /4-monopole antenna; Portable telephone model; Current distributions; Simulation; Time domain method Item Availability: CD-ROM. INSPEC 4353399 B9304-0170J-027 Doc Type: Conference Paper Title: Printing encapsulation systems (PES) of advanced multichip module and COB device Authors: Okuno, A.; Nagai, K.; Oyama, N.; Hashimoto, T.; Onishi, T.; Wakamoto, S.; Masui, K. Affiliation: Japan Rec Co. Ltd., Osaka, Japan Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 783-6 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0783$03.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical; Experimental Abstract: Continuous study of a printing encapsulation system (PES) for multichip module and COB (chip on board) led to optimal encapsulation resin properties. The authors have developed a printing encapsulation system (PES) of high reliability and quality, free of voids, and a thin and desirable encapsulation resin shape for an advanced COB device. Using this PES, it was possible to solve the problems in the printing encapsulation process to keep control of resin viscosity and other properties at open lid storage. It was possible to determine the suitable thixotropic property index. The authors developed a void-free process system which avoids the effects of heat shock and achieves moisture resistance improvement, and a short time curing system. (5 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits) Thesaurus: Encapsulation; Multichip modules Free Terms: Advanced multichip module; COB device; Printing encapsulation system; Optimal encapsulation resin properties; Control of resin viscosity; Open lid storage; Thixotropic property index; Void-free process system; Moisture resistance improvement; Short time curing system Item Availability: CD-ROM. INSPEC 4348138 B9303-2570-033 Doc Type: Conference Paper Title: New design for a leadframe used for high-speed transmission and high-power LSI package Authors: Mita, M.; Takagi, S.; Kumakura, T.; Yamaguchi; Tanaka, H. Affiliation: Hitachi Cable Ltd., Ibaraki, Japan Conf. Title: 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No.92CH3056-9) p. 458-66 Publisher: IEEE New York, NY, USA Date: 1992 xviii+1095 pp. Country of Publication: USA ISBN: 0 7803 0167 6 CCC: 0569 5503/92/0000-0458$03.00 Language: English Conf. Date: 18-20 May 1992 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical; Experimental Abstract: To meet the requirements of high speed driving LSI packages with powerful output, a combination leadframe has been developed which is made up of a two-metal-layer FPC (flexible printed circuit) and an outer leadframe. The use of thin copper foil minimizes the inner-lead pitch to 120 mu m. The combination structure of the FPC and leadframe greatly shortens the surface mounting. The developed method of joining the FPC to the leadframe using Au-Sn eutectic soldering is reliable at high temperatures and temperature cycles. This leadframe has some excellent characteristics. The electrical impedance of the leads can be easily controlled by rearrangement of lead widths, gaps, and dielectric insulation. The heat spreading effect by plain metal, which halved the apparent thermal resistance, is excellent. The adhesiveless copper clad laminate has a positive effect in preventing electromigration. (8 Refs.) Classification: B2570 (Semiconductor integrated circuits); B0170J (Product packaging) Thesaurus: Integrated circuit technology; Large scale integration; Packaging Free Terms: Thin Cu foil; Leadframe; High-speed transmission; High-power LSI package; High speed driving LSI; Two-metal-layer; Flexible printed circuit; Inner-lead pitch; Surface mounting; Electrical impedance; Heat spreading effect; Thermal resistance; Electromigration; 120 Micron; Au-Sn eutectic soldering; Cu clad laminate Numerical Index: Size 1.2E-04 m Chemical Index: Cu/int Cu/el; Au-Sn/int Au/int Sn/int Au/el Sn/el Item Availability: CD-ROM. INSPEC 4297177 B9301-2570-033 Doc Type: Conference Paper Title: Fabrication of high depth-to-width aspect ratio microstructures Authors: Engelmann, G.; Ehrmann, O.; Simon, J.; Reichl, H. Affiliation: Technol. der Mikroperipherik, Tech. Univ. Berlin, Germany Conf. Title: Proceedings. IEEE Micro Electro Mechanical Systems. An Investigation of Micro Structures, Sensors, Actuators, Machines and Robots(Cat. No.92CH3093-2) p. 93-8 Editors: Benecke, W.; Petzold, H.-C. Publisher: IEEE New York, NY, USA Date: 1992 xv+237 pp. Country of Publication: USA ISBN: 0 7803 0497 7 CCC: 0 7803 0497 7/92$03.00 Language: English Conf. Date: 4-7 Feb. 1992 Conf. Loc: Travemunde, Germany Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: It is reported that a 3-D fabrication process, based on sputtering of a thin-film plating base, on conventional UV lithography, and on electrochemical deposition of gold, makes microstructures of considerable height and resolution possible. The thin-film formation and the lithographic process are outlined, particular attention being paid to layer deposition and structure printing. The present resolution limit is about 4.5 mu m for a 30- mu m-thick resist. Much thicker layers (80 mu m) can be printed with reduced resolution. The results are discussed and process characteristics relevant in various applications are considered. (16 Refs.) Classification: B2570 (Semiconductor integrated circuits); B2550E (Surface treatment for semiconductor devices); B2550F (Metallisation and interconnection technology); B7230 (Sensing devices and transducers); B2550G (Lithography) Thesaurus: Electric actuators; Electric sensing devices; Electroplating; Metallisation; Micromechanical devices; Photolithography; Photoresists; Sputter etching Free Terms: RIE; Microsensors; Microactuators; Metallisation layers; Interdigital capacitor; High depth-to-width aspect ratio microstructures; 3-D fabrication process; Sputtering; Thin-film plating base; UV lithography; Electrochemical deposition; Structure printing; Au deposition Chemical Index: Au/sur Au/el Item Availability: CD-ROM. INSPEC 4288299 B9301-2220J-005 C9301-5440-006 Doc Type: Journal Paper Title: Ultra-Dense: an MCM-based 3-D digital signal processor Authors: Segelken, J.M.; Wu, L.J.; Lau, M.Y.; Tai, K.L.; Shively, R.R.; Grau, T.G. Affiliation: AT&T Bell Labs., Murray Hill, NJ, USA Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 15 Iss: 4 p. 438-43 Date: Aug. 1992 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/92/$03.00 Language: English Treatment: General/Review; Practical; Product review Abstract: The DSP3 Multiprocessor Project has produced a multi-GFLOP machine that is applicable to a variety of signal processing and pattern recognition problems. A companion program, the Ultra-Dense Project, is utilizing silicon-on-silicon multichip module (MCM) technology and innovative advanced packaging and physical design to achieve a parallel three-dimensional digital signal processor based on the DSP3. The authors present an overview and outline systems architecture the micro-interconnect technology (Si-on-Si MCM), and advances in physical design and packaging technology leading to an ultra-dense project demonstration. (4 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170J (Product packaging); C5440 (Multiprocessing systems); C5220P (Parallel architecture) Thesaurus: Multichip modules; Packaging; Parallel architectures; Parallel machines Free Terms: Parallel processors; 3-D digital signal processor; DSP3; Multiprocessor Project; Multi-GFLOP machine; Ultra-Dense Project; Overview; Systems architecture; Micro-interconnect technology; Si-on-Si MCM; Physical design; Packaging technology; Ultra-dense project demonstration; Si-Si modules Chemical Index: Si-Si/int Si/int Si/el Item Availability: CD-ROM. INSPEC 4260006 B9211-1265F-049 C9211-5130-012 Doc Type: Conference Paper Title: WASP 3: A real time signal and data processor Authors: Hedge, S.J.; Jalowiecki, I.P.; Lea, R.M. Affiliation: Aspex Microsystems, Uxbridge, UK Conf. Title: Proceedings. International Conference on Wafer Scale Integration (Cat. No.92CH3088-2) p. 105-14 Editors: Jain, V.K.; Wyatt, P.W. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xi+363 pp. Country of Publication: USA ISBN: 0 8186 2482 5 CCC: 0 8186 2482 5/92$01.00 Language: English Conf. Date: 22-24 Jan. 1992 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: General/Review Abstract: The WASP (WSI Associative String Processor) project is aimed at the production of embedded wafer-scale MPC (massively parallel computer) components, with performance, size, weight, power dissipation, and reliability parameters that are far superior to those obtained using conventional technology. WASP 3 heralds the progression to the WASP experimental program into its application demonstrator phase. As the first in a family of three devices, WASP 3 will demonstrate fundamental signal and data processing operations using a WASP device. Of at least equal significance will be the demonstration of the use of an industry-standard microelectronic packaging route for WASP devices. This establishes that WASP packaging has progressed far beyond the laboratory bench, and is maturing towards end-user standards. (9 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); C5130 (Microprocessor chips); C5135 (Digital signal processing chips); C5440 (Multiprocessing systems); C5220P (Parallel architecture) Thesaurus: Digital signal processing chips; Microprocessor chips; Packaging; Parallel architectures; Parallel machines; Real-time systems; VLSI Free Terms: Wafer scale integration; Real-time signal processor; Real-time data processor; WSI Associative String Processor; Embedded wafer-scale MPC; Massively parallel computer; Performance; Size; Weight; Power dissipation; Reliability; WASP 3; WASP experimental program; Application demonstrator phase; Industry-standard microelectronic packaging; WASP devices; WASP packaging Item Availability: CD-ROM. INSPEC 4230303 B9210-0170J-030 Doc Type: Conference Paper Title: Chip on board (COB) multichip modules design possibilities and manufacturing Authors: Clot, P. Conf. Title: Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium (Cat. No.91CH3043-7) p. 346-7 Publisher: IEEE New York, NY, USA Date: 1991 xvi+449 pp. Country of Publication: USA ISBN: 0 7803 0155 2 CCC: CH3043-7/91/0000-0346$01.00 Language: English Conf. Date: 16-18 Sept. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Application; General/Review Abstract: The author describes multichip module applications using COB for low-cost assembly of many dice on the same substrate even on both sides, to achieve full electronic circuitry miniaturization. Multichip modules on the FR4 PWB (printed wiring board) substrate are shown as an alternative to silicon on silicon, with in and out interconnection possibilities of particular note. This original packaging authorizes different shapes for modules. Surface mounted devices as well as leaded components are also added. Heat management is considered and explained through environmental test organization. Also, multichip silicon on silicon can be assembled on the same substrate to increase module performance and solve in and out connections from the main silicon dice. (0 Refs.) Classification: B0170J (Product packaging); B2210D (Printed circuit manufacture) Thesaurus: Cooling; Heat sinks; Modules; Packaging; Printed circuit manufacture Free Terms: FR4 PWB substrate; Heat management; Multichip modules; Manufacturing; COB; Low-cost assembly; Printed wiring board Item Availability: CD-ROM. INSPEC 4220496 B9210-6260-015 Doc Type: Journal Paper Title: Optical module with a silica-based planar lightwave circuit for fiber-optic subscriber systems Authors: Terui, H.; Kominato, T.; Yoshino, K.; Ichikawa, F.; Hata, S.; Sekine, S.; Kobayashi, M.; Yoshida, J.; Okada, K. Affiliation: NTT Opto-Electron. Labs., Ibaraki, Japan Journal: IEEE Photonics Technology Letters Vol: 4 Iss: 6 p. 660-2 Date: June 1992 Country of Publication: USA ISSN: 1041-1135 CODEN: IPTLEL CCC: 1041-1135/92/$03.00 Language: English Treatment: Practical Abstract: An optical module for use in both 1.3- mu m signal transmitting/receiving and 1.3/1.5- mu m signal multi/demultiplexing was developed by assembling a silica-based planar lightwave circuit composed of wavelength division multiplexing (WDM) and optical coupler circuits, a miniature laser diode (LD) submodule, and a photodiode (PD) submodule. The module exhibits 0-dBm optical output at 32-mA driving current and a responsivity of 0.3 A/W for a 1.3- mu m band, and an insertion loss of 0.9-2.0 dB for a 1.5- mu m band. (7 Refs.) Classification: B6260 (Optical links and equipment); B6230 (Switching centres and equipment); B4270 (Integrated optoelectronics); B4320J (Semiconductor lasers); B4250 (Photoelectric devices) Thesaurus: Frequency division multiplexing; Integrated optoelectronics; Multiplexing equipment; Optical communication equipment; Optical links; Photodiodes; Semiconductor junction lasers; Subscriber loops; Transceivers Free Terms: IR; Silica-based planar lightwave circuit; Fiber-optic subscriber systems; Optical module; Signal transmitting/receiving; Signal multi/demultiplexing; Wavelength division multiplexing; WDM; Optical coupler circuits; Miniature laser diode; Submodule; Photodiode; Optical output; Driving current; Responsivity; Insertion loss; 1.3 Micron; 1.5 Micron; 32 MA; 0.9 To 2 dB Numerical Index: Wavelength 1.3E-06 m; Wavelength 1.5E-06 m; Current 3.2E-02 A; Loss 9.0E-01 to 2.0E+00 dB Chemical Index: SiO2/int O2/int Si/int O/int SiO2/ss O2/ss Si/ss O/ss Item Availability: CD-ROM. INSPEC 4155340 B9206-2220J-013 Doc Type: Conference Paper Title: The establishment of a multi-chip module foundry at RIT Authors: Pearson, R.E.; Mukund, P.R. Affiliation: Rochester Inst. of Technol., NY, USA Conf. Title: Proceedings. Ninth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.91CH3027-0) p. 238-41 Publisher: IEEE New York, NY, USA Date: 1991 262 pp. Country of Publication: USA ISBN: 0 7803 0109 9 CCC: 0 7803 0109 9/91/0000-0238$01.00 Language: English Conf. Date: 12-14 June 1991 Conf. Loc: Melbourne, FL, USA Conf. Sponsor: IEEE; SEMATECH; Florida Inst. Technol Treatment: General/Review Abstract: Faculty from the Rochester Institute of Technology's (RIT's) College of Engineering and College of Science have formed a group aimed at advanced multichip module (MCM) packaging of high-speed electronics systems. The authors discuss the cooperation between university, industry, and ultimately the government in an attempt to open up the field of MCM design, fabrication, and use in an educational setting. This group has begun fabrication of both a process evaluation module and actual application-specific modules. The key aspect of the RIT MCM effort is the establishment of an MCM foundry at RIT. The foundry would not be a large-volume foundry, but would provide for internal and supported external MCM fabrication needs. RIT offers a unique fabrication opportunity for MCMs and would like to work with other companies and universities to maximize the exposure of this technology. (7 Refs.) Classification: B2220J (Hybrid integrated circuits); B0170E (Production facilities and engineering) Thesaurus: Hybrid integrated circuits Free Terms: University/industry cooperation; Rochester Institute of Technology; Multi-chip module foundry; High-speed electronics systems; MCM design; Fabrication; Educational setting; Process evaluation module; Application-specific modules; MCM foundry; RIT Item Availability: CD-ROM. INSPEC 4127263 B9205-1265D-029 Doc Type: Conference Paper Title: A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs Authors: Sakao, M.; Kasai, N.; Ishijima, T.; Ikawa, E.; Watanabe, H.; Terada, K.; Kikkawa, T. Affiliation: NEC Corp., Tokyo, Japan Conf. Title: International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4) p. 655-8 Publisher: IEEE New York, NY, USA Date: 1990 986 pp. Country of Publication: USA CCC: CH2865-4/90/0000-0655$01.00 Language: English Conf. Date: 9-12 Dec. 1990 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m. (10 Refs.) Classification: B1265D (Memory circuits); B2570F (Other MOS integrated circuits) Thesaurus: Cellular arrays; DRAM chips; MOS integrated circuits; VLSI Free Terms: Polysilicon storage node; Capacitor-over-bit-line; COB; Hemispherical-grain storage node; Storage capacitance; Optical delineation; COB cell; Dielectric film; Storage node height; 0.4 Micron; 64 Mbit; 30 FF Numerical Index: Size 4.0E-07 m; Storage capacity 6.7E+07 bit; Capacitance 3.0E-14 F Item Availability: CD-ROM. INSPEC 4117874 B9205-8110-013 Doc Type: Conference Paper Title: Determination of a three phase harmonic load model using background harmonic levels Authors: Palmer, E.W.; Ledwich, G.F. Affiliation: Sch. of Electr. & Electron. Syst. Eng., Queensland Univ. of Technol., Brisbane, Qld., Australia Conf. Title: APSCOM-91. 1991 International Conference on Advances in Power System Control, Operation and Management (Conf. Publ. No.348) p. 727-36 vol.2 Publisher: IEE Hong Kong Date: 1991 2 vol. xvii+932 pp. Country of Publication: Hong Kong ISBN: 0 86341 246 7 Availability: IEE, London, UK Language: English Conf. Date: 5-8 Nov. 1991 Conf. Loc: Hong Kong Treatment: Theoretical/Mathematical Abstract: A noninvasive method is described for measuring three phase harmonic load models incorporating harmonic sources for composite power system loads. The method relies upon the presence of a dominant harmonic source close to the load being modelled and constancy of any harmonic sources within the load during the period of measurement. The method is shown to perform quite well in a laboratory test, however it is shown to fail when applied to the modelling of an industrial load due to the unexpected presence within the load of a dominant, time-dependant harmonic source. It is recommended that the method described be restricted to use with loads shown beforehand to satisfy the basic modelling assumptions regarding sources within the load and that invasive techniques be used in cases where these assumptions are violated. (8 Refs.) Classification: B8110 (Power systems) Thesaurus: Harmonics; Load [electric]; Power systems Free Terms: Three phase harmonic load model; Background harmonic levels; Noninvasive method; Composite power system loads; Industrial load; Time-dependant harmonic source Item Availability: CD-ROM. INSPEC 4076734 B9203-1265F-036 C9203-5220P-015 Doc Type: Conference Paper Title: WSI interconnect issues: practical experience gained on the WASP project Authors: Hedge, S.J.; Jalowiecki, I.P.; Lea, R.M. Affiliation: Aspex Microsyst., Brunel Univ., Uxbridge, UK Conf. Title: 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9) p. 263-9 Editors: Little, M.J.; Jain, V.K. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9126 3 Language: English Conf. Date: 29-31 Jan. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: General/Review Abstract: The problems of external interfacing and internal interconnection for WSI (wafer scale integration) devices are considered. In particular, the WASP (WSI associative string processor) 2A device is examined in detail, and practical results are presented. Analysis of the experimental on-wafer interconnection included on WASP 2A has shown that, given simple layout precautions, a high yield can be obtained for non-defect-tolerant buses. However, it is also apparent that practical experience concerning the defect modes of these buses is important in the design of any defect tolerance strategy for yield improvement. Results from using WASP 2A have shown that defect and fault tolerance may be cost-effectively implemented at the level of the wafer interface, allowing for the recovery from defects and in-service failures, and substantially increasing the projected yield of this crucial wafer component. (3 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); B0170J (Product packaging); C5220P (Parallel architecture); C5440 (Multiprocessing systems); C5130 (Microprocessor chips) Thesaurus: Fault tolerant computing; Microprocessor chips; Packaging; Parallel processing; VLSI Free Terms: WSI interconnect issues; WASP project; External interfacing; Internal interconnection; Wafer scale integration; WSI associative string processor; Practical results; On-wafer interconnection; WASP 2A; Layout precautions; High yield; Non-defect-tolerant buses; Defect modes; Defect tolerance; Yield improvement; Fault tolerance; Recovery from defects Item Availability: CD-ROM. INSPEC 4076466 B9203-0170J-015 Doc Type: Conference Paper Title: COB and SMD on FR4 and flex PWB (printed wired board) for miniaturized modules Authors: Clot, P. Affiliation: Valtronic SA, Les Charbonnieres, Switzerland Conf. Title: 8th IEMT 1990. International Electronic Manufacturing Technology Symposium (Cat. No.90CH2833-2) p. 479-84 Publisher: IEEE New York, NY, USA Date: 1990 viii+515 pp. Country of Publication: USA CCC: CH2833-2/90/0000-0479$01.00 Language: English Conf. Date: 7-9 May 1990 Conf. Loc: Baveno, Italy Conf. Sponsor: IEEE Treatment: General/Review; Practical Abstract: The authors describe an original mode of packaging using COB (chip-on-board) and SMD (surface-mount-devices) technology for many electronic applications when miniaturization and low weight are conditions. Attention is given to the wiring principle, the construction, the components, and the assembly. (0 Refs.) Classification: B0170J (Product packaging); B2210D (Printed circuit manufacture); B2210B (Printed circuit layout and design) Thesaurus: Modules; Packaging; Printed circuit design; Printed circuit manufacture; Surface mount technology Free Terms: COB; SMD; FR4; Flex PWB; Printed wired board; Miniaturized modules; Mode of packaging; Chip-on-board; Surface-mount-devices; Miniaturization; Low weight; Wiring principle; Construction; Components; Assembly Item Availability: CD-ROM. INSPEC 4014784 B91075838 Doc Type: Journal Paper Title: The ellipsoidal technique for design centering and region approximation Authors: Abdel-Malek, H.L.; Hassan, A.-K.S.O. Affiliation: Dept. of Eng. Phys. & Math., Cairo Univ., Giza, Egypt Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol: 10 Iss: 8 p. 1006-14 Date: Aug. 1991 Country of Publication: USA ISSN: 0278-0070 CODEN: ITCSDI CCC: 0278-0070/91/0800-1006$01.00 Language: English Treatment: Theoretical/Mathematical Abstract: A technique for design centering and feasible region approximation that is based on generating a sequence of ellipsoids of decreasing volume and preserves the property of containing a bounded convex feasible region is introduced. The technique converges to an ellipsoid the center of which is the proposed design center. The ellipsoid matrix can be used to give what is called a preferable covariance matrix, assuming a multinormal distribution of parameters. This covariance matrix is preferred since it significantly increases the production yield for the feasible region under consideration. In addition, an ellipsoidal region approximation can be obtained by scaling the final ellipsoid, which allows an inexpensive yield estimate using the Monte Carlo method. Numerical and practical examples are considered. (17 Refs.) Classification: B1130B (Computer-aided circuit analysis and design); B0240G (Monte Carlo methods); B0210 (Algebra) Thesaurus: Circuit CAD; Matrix algebra; Monte Carlo methods Free Terms: CAD; Ellipsoidal technique; Design centering; Region approximation; Bounded convex feasible region; Covariance matrix; Yield estimate; Monte Carlo method Item Availability: CD-ROM. INSPEC 3976828 A91121814 Doc Type: Conference Paper Title: Plasma density measurements in PBFA II opening switch configurations Authors: Weber, B.V.; McDaniel, D.H.; Rochau, G.E. Affiliation: US Naval Res. Lab., Washington, DC, USA Conf. Title: Conference Record - Abstracts. 1990 IEEE International Conference on Plasma Science (Cat. No.90CH2857-1) p. 187-8 Publisher: IEEE New York, NY, USA Date: 1990 231 pp. Country of Publication: USA Language: English Conf. Date: 21-23 May 1990 Conf. Loc: Oakland, CA, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: Summary form only given. Several opening switch configurations have been tested on the PBFA II (Particle Beam Fusion Accelerator II). The plasma density has been measured in a separate vacuum chamber for three opening switch configurations. The measurements were made using a 140-GHz microwave interferometer with quadrature phase detection. Faraday cups were used as a common monitor to correlate the test chamber measurements and the PBFA II experiments. The three opening switch configurations utilize flashboard plasma sources, where plasma is generated by discharging a capacitor through an array of flashover gaps on a carbon-coated insulator. The three configurations differ by the flashboards used, the electrical circuit used to power the flashboard, and the geometrical arrangement. Estimates of plasma displacement by J*B forces, conduction current scaling, and opening mechanisms were obtained. (1 Refs.) Classification: A5270G (Radiofrequency and microwave plasma diagnostic techniques); A5275K (Plasma switches); A5225L (Plasma temperature and density); A2852L (Fusion reactor instrumentation) Thesaurus: Fusion reactor instrumentation; Plasma density; Plasma diagnostics; Plasma switches Free Terms: C-coated insulator; Plasma density measurement; PBFA II opening switch configurations; Particle Beam Fusion Accelerator II; Vacuum chamber; Opening switch configurations; Microwave interferometer; Quadrature phase detection; Faraday cups; Monitor; Test chamber measurements; Flashboard plasma sources; Discharging; Capacitor; Array; Flashover gaps; Electrical circuit; Plasma displacement; J*B forces; Conduction current scaling; Opening mechanisms; 140 GHz; C Numerical Index: Frequency 1.4E+11 Hz Chemical Index: C/sur C/el Item Availability: CD-ROM. INSPEC 3976827 A91121840 Doc Type: Conference Paper Title: Performance of magnetically-injected-plasma opening switches on the particle beam fusion accelerator II (PBFA II) Authors: Rochau, G.E.; McDaniel, D.H.; Mendel, C.W.; Sweeney, M.A.; Moore, W.B.S.; Mowrer, G.R.; Zagar, D.M. Affiliation: Sandia Nat. Lab., Albuquerque, NM, USA Conf. Title: Conference Record - Abstracts. 1990 IEEE International Conference on Plasma Science (Cat. No.90CH2857-1) p. 187 Publisher: IEEE New York, NY, USA Date: 1990 231 pp. Country of Publication: USA Language: English Conf. Date: 21-23 May 1990 Conf. Loc: Oakland, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: Summary form only given, as follows. Plasma opening switch (POS) experiments have been performed on the PBFA II to develop a switch which will provide voltage and power gain to an applied-B lithium ion diode. These experiments have successfully coupled power to electron and ion beam diodes using a magnetically-injected-plasma (MIP) POS. Carbon plasma with electron densities of 1*10/sup 12/ to 2*10/sup 13//cm/sup 3/ has been injected from the anode into the 8-cm gap of the 20- Omega magnetically insulated transmission line (MITL) of PBFA II along a B/sub r.z/ magnetic field. The MIP switch uses the inertia of the plasma to keep the switch closed and the magnetic pressure of B/sub 0/ from the conduction current to open the switch. The configuration of the injecting magnetic field and the plasma source, has a significant effect on the efficiency of coupling power to high-impedance loads. Plasma near the center of the injecting magnetic field limits the opening impedance of the switch and subsequently the power delivered to the load. The axial location of the switch with respect to the load has also been identified as a critical parameter in increasing the coupling efficiency. A length of 10 to 20 cm of MITL between the POS and the load has increased the power delivered to the load. (0 Refs.) Classification: A5275K (Plasma switches); A2852J (Fusion reactor theory and design); A2852L (Fusion reactor instrumentation) Thesaurus: Fusion reactor instrumentation; Fusion reactor theory and design; Particle accelerators; Plasma switches Free Terms: Electron beam diode; Performance; Power coupling efficiency; Magnetically-injected-plasma opening switches; Particle beam fusion accelerator II; PBFA II; Voltage; Power gain; Applied-B lithium ion diode; Ion beam diodes; Electron densities; Gap; Magnetically insulated transmission line; MITL; Inertia; Magnetic pressure; Conduction current; Configuration; Injecting magnetic field; Plasma source; 8 Cm; 10 To 20 cm; Li; C plasma Numerical Index: Size 8.0E-02 m; Size 1.0E-01 to 2.0E-01 m Chemical Index: Li/el; C/el Item Availability: CD-ROM. INSPEC 3976826 A91121839 B91066931 Doc Type: Conference Paper Title: Long condition time POS experiments on MITE Authors: Woodall, H.N.; McDaniel, D.H.; Mendel, C.W.; Rochau, G.E.; Zagar, D.M.; Simpson, W.W.; Zuchowski, N.P. Affiliation: Sandia Nat. Lab., Albuquerque, NM, USA Conf. Title: Conference Record - Abstracts. 1990 IEEE International Conference on Plasma Science (Cat. No.90CH2857-1) p. 187 Publisher: IEEE New York, NY, USA Date: 1990 231 pp. Country of Publication: USA Language: English Conf. Date: 21-23 May 1990 Conf. Loc: Oakland, CA, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: Summary form only given. MITE is a power flow testbed that has been modified to conduct experiments in high-power plasma opening switch (POS) technology and apply this technology to inertial confinement fusion. The goal of the experiment is to develop a POS that conducts megampere currents for 300 ns, then opens in 5-10 ns. MITE/POS is an advanced power flow experiment that uses a magnetically insulated transmission line (MITL) as the inductive energy store and as a means to shape the output pulse. This experiment demonstrates that a simplified, lower-cost facility can be built by eliminating water pulse-forming lines and water switching. The disadvantage is that a new technology, the triggered POS, must be implemented. The triggered POS is necessary for synchronization of multiple modules with a long-conduction-time POS. The MITE facility has been modified to drive a 250-nH. 16.6- Omega MITL at 0.9 MA to accommodate this power flow experiment. A MITL inductive energy storage of 101 kJ is available for POS switching to a matched load. Experiments leading to the development of the triggered POS have been conducted using segmented flashboards and magnetic-field controlled plasma sources. (0 Refs.) Classification: A5275K (Plasma switches); A2852J (Fusion reactor theory and design); B8370 (Switchgear); B8350 (Transformers and reactors); B8470 (Other energy storage) Thesaurus: Fusion reactor theory and design; Inductive energy storage; Plasma switches; Pulsed power technology; Transmission lines Free Terms: MITE; Power flow testbed; High-power plasma opening switch; Inertial confinement fusion; Megampere currents; Magnetically insulated transmission line; Inductive energy store; Water pulse-forming lines; Water switching; Triggered POS; Synchronization; Long-conduction-time; Inductive energy storage; Matched load; Segmented flashboards; Magnetic-field controlled plasma sources; 300 Ns; 5 To 10 ns; 0.9 MA; 101 KJ Numerical Index: Time 3.0E-07 s; Time 5.0E-09 to 1.0E-08 s; Current 9.0E+05 A; Energy 1.01E+05 J Item Availability: CD-ROM. INSPEC 3976132 B91063079 C91060768 Doc Type: Conference Paper Title: Datapath generator based on gate-level symbolic layout Authors: Matsumoto, N.; Watanabe, Y.; Usami, K.; Sugeno, Y.; Hatada, H.; Mori, S. Affiliation: Toshiba Corp., Kawasaki, Japan Conf. Title: 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4) p. 388-93 Publisher: IEEE New York, NY, USA Date: 1990 xxi+743 pp. Country of Publication: USA ISBN: 0 89791 363 9 CCC: 0738-100X/90/0000-0388$1.00 Language: English Conf. Date: 24-28 June 1990 Conf. Loc: Orlando, FL, USA Conf. Sponsor: ACM; IEEE Treatment: Practical Abstract: A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21 K-transistor data-path whose density is 5.64 KTr/mm/sup 2/, greater than the 5.38 KTr/mm/sup 2/ of a hand-crafted datapath, was generated using 1- mu m CMOS technology. (18 Refs.) Classification: B2570D (CMOS integrated circuits); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing) Thesaurus: Circuit layout CAD; CMOS integrated circuits; Large scale integration Free Terms: Gate-level symbolic layout; Data-path generator; LSI mask layouts; Bit-and-row-slicing technique; CMOS technology; 1 Micron Numerical Index: Size 1.0E-06 m Item Availability: CD-ROM. INSPEC 3958005 B91055259 C91052458 Doc Type: Conference Paper Title: A practical WSI experimental programme Authors: Jalowiecki, I.P.; Hedge, S.J.; Lea, R.M. Affiliation: Brunel Univ., Uxbridge, UK Conf. Title: IEE Colloquium on 'Wafer Scale Integration' (Digest No.111) p. 7/1-3 Publisher: IEE London, UK Date: 1991 32 pp. Country of Publication: UK Language: English Conf. Date: 28 May 1991 Conf. Loc: London, UK Conf. Sponsor: IEE Treatment: Practical Abstract: At Brunel University, research has been underway for several years to assess the architectural, electrical and physical benefits and constraints of the WASP wafer-scale Associative String Processor (ASP). This is intended to implement a massively parallel processor entirely within the constraints of WSI. WASP 1 and WASP 2 were the technology demonstrators of the UK funded Alvey programme (starting 1984), researching fundamental design methodologies for WSI. They are both examples of the Associative String Processor (ASP) architecture, developed by Brunel University. Further demonstrators are currently funded by a 3/sup 1///sub 2/-year US ONR IS&T programme (starting 1987), involving both further technology demonstration, applications research and fundamental packaging and manufacturing design issues. (0 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); C5130 (Microprocessor chips); C5220 (Computer architecture) Thesaurus: Microprocessor chips; Parallel architectures; VLSI Free Terms: Brunel University; WASP wafer-scale Associative String Processor; Massively parallel processor; WSI; WASP 1; WASP 2; Design methodologies; Packaging; Manufacturing design Item Availability: CD-ROM. INSPEC 3897488 B91037028 Doc Type: Conference Paper Title: Package design for high-speed low-cost ASIC LSIs Authors: Otsuka, K.; Shirai, Y.; Miwa, T.; Nakano, T.; Yamagiwa, A.; Hatada, T.; Tsuboi, T. Affiliation: Hitachi Ltd., Tokyo, Japan Conf. Title: 1990 Proceedings. 40th Electronic Components and Technology Conference (Cat. No.90CH2893-6) p. 1078-84 vol.2 Publisher: IEEE New York, NY, USA Date: 1990 2 vol. xvi+1125 pp. Country of Publication: USA CCC: 0569-5503/90/0000-1078$01.00 Language: English Conf. Date: 20-23 May 1990 Conf. Loc: Las Vegas, NV, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: Cofired alumina ceramic, alumina-based Cu/polyimide thin films, and plastic PGAs (pin-grid-arrays) are compared in terms of electrical and thermal characteristics and cost. Plastic PGA with the cavity down and a three-layer structure is shown to be the best way to meet the requirement of over 50-MHz signal transmission, thermal resistance and cost. The best results on the 592-pin plastic PGA package and its simulation results are described. (10 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits) Thesaurus: Application specific integrated circuits; Ceramics; Integrated circuit technology; Large scale integration; Packaging; Polymer films Free Terms: Electrical characteristics; Cofired alumina ceramic; ASIC LSIs; Alumina-based Cu/polyimide thin films; Plastic PGAs; Thermal characteristics; Cost; Signal transmission; Thermal resistance; Simulation results; Al/sub 2/O/sub 3/ Chemical Index: Al2O3/sur Al2/sur Al/sur O3/sur O/sur Al2O3/bin Al2/bin Al/bin O3/bin O/bin Item Availability: CD-ROM. INSPEC 3891700 B91037468 Doc Type: Journal Paper Title: Tunability of biquadratic responses Authors: Abdel-Malek, H.L. Affiliation: Dept. of Eng. Phys. & Math., Cairo Univ., Giza, Egypt Journal: IEEE Transactions on Circuits and Systems Vol: 38 Iss: 2 p. 223-7 Date: Feb. 1991 Country of Publication: USA ISSN: 0098-4094 CODEN: ICSYBT CCC: 0098-4094/91/0200-0223$01.00 Language: English Treatment: Theoretical/Mathematical Abstract: A simple and efficient criterion for the selection of tuning parameters is introduced. This criterion uses the coefficients of the biquadratic response function exhibited in the frequency domain by certain lumped linear circuits. The tuning criterion takes into consideration the required large range of response variation with an associated small change in the tuning parameter and is based on an overlook of the biquadratic response rather than the locality of the first-order sensitivities. The criterion is justified mathematically and applied to practical examples. Tolerances are assumed in circuit elements, and tunability using this criterion is checked. The post-tuning yield is evaluated and compared with that obtained by other methods. (7 Refs.) Classification: B1150D (Lumped linear networks); B1270 (Filters and other networks) Thesaurus: Active filters; Frequency response; Linear network analysis; Lumped parameter networks; Passive filters; Tuning Free Terms: Selection criteria; Frequency domain response function; Biquadratic responses; Tuning parameters; Lumped linear circuits; Tunability; Post-tuning yield Item Availability: CD-ROM. INSPEC 3863859 B91024813 C91028620 Doc Type: Conference Paper Title: The WASP 2 WSI massively parallel processor demonstrators Authors: Jalowiecki, I.P.; Hedge, S.J. Affiliation: Brunel Univ., Uxbridge, UK Conf. Title: Proceedings of the IEEE 1990 Custom Integrated Circuits Conference (Cat. No.90CH2860-5) p. 17.1/1-4 Publisher: IEEE New York, NY, USA Date: 1990 xxvi+796 pp. Country of Publication: USA CCC: CH2860-5/90/0000-0091$1.00 Language: English Conf. Date: 13-16 May 1990 Conf. Loc: Boston, MA, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: WASP 1 is reviewed, and the WASP 2a and WASP 2b wafer-scale integration (WSI) massively parallel processor technology demonstrators, implemented in standard CMOS technology, are discussed. These latter devices are defect-tolerant arrays of 864 and 6048 processing elements and integrate 1.26 M transistors (4 cm*4 cm) and 7.87 M transistors (10 cm*10 cm). The two variants (WASP 2a and WASP 2b) are examples of the associative string processor (ASP) architecture, developed at Brunel University. WASP 2a/2b, as well as their successful predecessor, WASP 1, are the technology demonstrators of the UK Alvey WSI program. (4 Refs.) Classification: B2570D (CMOS integrated circuits); B1265F (Microprocessors and microcomputers); C5220 (Computer architecture); C5440 (Multiprocessing systems) Thesaurus: CMOS integrated circuits; Microprocessor chips; Multiprocessing systems; Parallel architectures; Parallel machines; VLSI Free Terms: WSI associative string processors; WASP 2; WSI massively parallel processor demonstrators; WASP 1; WASP 2a; WASP 2b; Wafer-scale integration; Standard CMOS technology; Defect-tolerant arrays; Associative string processor; Brunel University; WASP; Technology demonstrators; UK Alvey WSI program; 4 Cm; 10 Cm Numerical Index: Size 4.0E-02 m; Size 1.0E-01 m Item Availability: CD-ROM. INSPEC 3788068 B91002216 C91003151 Doc Type: Conference Paper Title: The WASP demonstrator programme: the engineering of a wafer-scale system Authors: Jalowiecki, I.P.; Hedge, S.J. Affiliation: Aspex Microsyst. Ltd., Brunel Univ., Uxbridge, UK Conf. Title: 1990 Proceedings. International Conference on Wafer Scale Integration (Cat. No.90CH2814-2) p. 43-9 Editors: Brewer, J.; Little, M.J. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1990 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9013 5 CCC: CH2814-2/90/0000/0043$01.00 Language: English Conf. Date: 23-25 Jan. 1990 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Experimental Abstract: The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2). (3 Refs.) Classification: B2570 (Semiconductor integrated circuits); B1265F (Microprocessors and microcomputers); C5220 (Computer architecture); C5130 (Microprocessor chips) Thesaurus: Cellular arrays; Integrated circuit technology; Microprocessor chips; Parallel architectures; VLSI Free Terms: WASP demonstrator programme; Wafer-scale system; Brunel University; Aspex Microsystems; WSI Associative String Processor; Wafer-Scale Parallel Processing systems; Associative String Processor; Fine-grain architecture; Test chip experimentation; Engineering data; Proof of principle; Demonstrator programme; Test results Item Availability: CD-ROM. INSPEC 3781418 B91002921 Doc Type: Conference Paper in Journal Title: LED array modules by new technology microbump bonding method Authors: Hatada, K.; Fujimoto, H.; Ochi, T.; Ishida, Y. Affiliation: Matsushita Electr. Ind. Co. Ltd., Osaka, Japan Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 13 Iss: 3 p. 521-7 Date: Sept. 1990 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/90/0900-0521$01.00 Language: English Conf. Title: 1989 7th IEEE/CHMT Intenational Electronic Manufacturing Technology Symposium Conf. Date: 25-27 Sept. 1989 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: New development; Practical; Experimental Abstract: An LED array module was developed by using the microbump bonding method by which the electrodes of LSI chips and circuit substrate are press-bonded by utilizing the shrinkage stress produced in a light setting insulating resin. The LED array module has a resolution of 400 DPI, and is constructed by face-down mounting of 54 each of the LED chips and driver LSIs on a glass substrate. These LED chips, having an electrode pitch of 63.5 mu m, are disposed on the glass substrate at a pitch of 10 mu m. A dedicated bonder was developed for this assembling work. A report on the LED array module assembling process and the construction of a bonder is presented. (4 Refs.) Classification: B4260D (Light emitting diodes); B2240 (Microassembly techniques) Thesaurus: Large scale integration; Lead bonding; Light emitting diodes; Modules Free Terms: Press bonding; LED array modules; Microbump bonding method; LSI chips; Circuit substrate; Shrinkage stress; Light setting insulating resin; Face-down mounting; Glass substrate; Module assembling process; 635 Micron; 10 Micron Numerical Index: Size 6.35E-04 m; Size 1.0E-05 m Item Availability: CD-ROM. INSPEC 3668533 B90044191 C90046372 Doc Type: Conference Paper Title: WASP: a demonstrated wafer scale technology Authors: Jalowiecki, I.P.; Hedge, S.J.; Lea, R.M. Affiliation: Brunel Univ., Uxbridge, UK Conf. Title: UK IT 1990 Conference (Conf. Publ. No.316) p. 184-9 Publisher: IEE London, UK Date: 1990 xi+441 pp. Country of Publication: UK Language: English Conf. Date: 19-22 March 1990 Conf. Loc: Southampton, UK Treatment: Practical Abstract: The authors review WASP 1 and discuss the WASP 2a and WASP 2b wafer scale integration (WSI) massively parallel processor technology demonstrators, implemented in standard CMOS technology. These latter devices are defect-tolerant arrays of 864 and 6480 processing elements and integrate 1.26 M transistors (4 cm*4 cm) and 8.43 M transistors (10 cm*10 cm). The two variants (WASP 2a and WASP 2b) are examples of the associative string processor (ASP) architecture, developed by Brunel University. WASP 2a/2b, as well as their successful predecessor, WASP 1, are the technology demonstrators of the UK Alvey WSI programme. (7 Refs.) Classification: B2570D (CMOS integrated circuits); C5440 (Multiprocessing systems); C5220 (Computer architecture); C5470 (Performance evaluation and testing) Thesaurus: CMOS integrated circuits; Fault tolerant computing; Parallel architectures; Parallel machines; VLSI Free Terms: ASP architecture; WSI; WASP 1; WASP 2a; WASP 2b wafer scale integration; Massively parallel processor technology demonstrators; Standard CMOS technology; Defect-tolerant arrays; Processing elements; Transistors; Associative string processor; Technology demonstrators; UK Alvey WSI programme Item Availability: CD-ROM. INSPEC 5163453 B9603-0170J-006 Doc Type: Journal Paper Title: Thermal characterization of vertical multichip modules MCM-V Authors: Cahill, C.; Compagno, A.; O`Donovan, J.; Slattery, O.; O`Mathuna, S.C.; Barrett, J.; Serthelon, I.; Val, C.; Tigners, J.-P.; Stern, J.; Ivey, P.; Masgrangeas, M.; Coello-Vera, A. Affiliation: Nat. Microelectron. Res. Centre, Cork, Ireland Journal: IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A Vol: 18 Iss: 4 p. 765-72 Publisher: IEEE Date: Dec. 1995 Country of Publication: USA ISSN: 1070-9886 CODEN: IMTAEZ CCC: 1070-9886/95/$04.00 Language: English Treatment: Practical; Experimental Abstract: This paper describes the thermal characterization of a vertical multichip module (MCM-V) technology. The MCM-V technology encloses a stack of IC`s in a three dimensional cube of plastic molding compound, with the inter-chip electrical connections made on the outside faces of the tube. Thermal measurements mere carried out on two different sized modules containing eight specially designed package evaluation test chips. Steady state and transient thermal results are presented. Simulation results are shown for two applications manufactured using the MCM-V technology; a 2 W, 16 chip 256 MBit DRAM module and a 3 W: 9 chip image processing system. (16 Refs.) Classification: B0170J (Product packaging); B2250 (Multichip modules) Thesaurus: Multichip modules; Plastic packaging; Thermal analysis; Transient analysis Free Terms: Vertical multichip modules; MCM-V; Thermal characterization; Three dimensional cube; Plastic molding compound; Inter-chip electrical connections; Package evaluation test chips; Steady state results; Transient thermal results; DRAM module; Image processing system; 2 W; 3 W Numerical Index: Power 2.0E+00 W; Power 3.0E+00 W Item Availability: CD-ROM. INSPEC 5163453 B9603-0170J-006 Doc Type: Journal Paper Title: Thermal characterization of vertical multichip modules MCM-V Authors: Cahill, C.; Compagno, A.; O`Donovan, J.; Slattery, O.; O`Mathuna, S.C.; Barrett, J.; Serthelon, I.; Val, C.; Tigners, J.-P.; Stern, J.; Ivey, P.; Masgrangeas, M.; Coello-Vera, A. Affiliation: Nat. Microelectron. Res. Centre, Cork, Ireland Journal: IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A Vol: 18 Iss: 4 p. 765-72 Publisher: IEEE Date: Dec. 1995 Country of Publication: USA ISSN: 1070-9886 CODEN: IMTAEZ CCC: 1070-9886/95/$04.00 Language: English Treatment: Practical; Experimental Abstract: This paper describes the thermal characterization of a vertical multichip module (MCM-V) technology. The MCM-V technology encloses a stack of IC`s in a three dimensional cube of plastic molding compound, with the inter-chip electrical connections made on the outside faces of the tube. Thermal measurements mere carried out on two different sized modules containing eight specially designed package evaluation test chips. Steady state and transient thermal results are presented. Simulation results are shown for two applications manufactured using the MCM-V technology; a 2 W, 16 chip 256 MBit DRAM module and a 3 W: 9 chip image processing system. (16 Refs.) Classification: B0170J (Product packaging); B2250 (Multichip modules) Thesaurus: Multichip modules; Plastic packaging; Thermal analysis; Transient analysis Free Terms: Vertical multichip modules; MCM-V; Thermal characterization; Three dimensional cube; Plastic molding compound; Inter-chip electrical connections; Package evaluation test chips; Steady state results; Transient thermal results; DRAM module; Image processing system; 2 W; 3 W Numerical Index: Power 2.0E+00 W; Power 3.0E+00 W Item Availability: CD-ROM. INSPEC 5156571 C9602-5540-006 Doc Type: Journal Paper Title: 3D graphics processor chip set Authors: Awaga, M.; Ohtsuka, T.; Yoshizawa, H.; Sasaki, S. Affiliation: Fujitsu Labs. Ltd., Kawasaki, Japan Journal: IEEE Micro Vol: 15 Iss: 6 p. 37-45 Publisher: IEEE Date: Dec. 1995 Country of Publication: USA ISSN: 0272-1732 CODEN: IEMIDZ CCC: 0272-1732/95/$04.00 Language: English Treatment: Practical Abstract: Increasingly, 3D graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM, and video production. Some LSIs provide rendering capabilities, but require an additional CPU to perform essential geometry transformations. Fujitsu`s chip set solves that problem using two processors to render 300,000 polygons per second (for flat-shaded triangles with texture)-performance comparable to that of advanced game machines. (3 Refs.) Classification: C5540 (Terminals and graphic displays); C5130 (Microprocessor chips); C6130B (Graphics techniques); C5150 (Other circuits for digital computers) Thesaurus: Computer graphic equipment; Computer graphics; Microprocessor chips Free Terms: 3D graphics; Graphics processor chip set; Fujitsu; 300,000 Polygons per second Item Availability: CD-ROM. INSPEC 5156570 C9602-5320G-003 Doc Type: Journal Paper Title: Advances in DRAM interfaces Authors: Kumanoya, M.; Ogawa, T.; Inoue, K. Affiliation: LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Hyogo, Japan Journal: IEEE Micro Vol: 15 Iss: 6 p. 30-6 Publisher: IEEE Date: Dec. 1995 Country of Publication: USA ISSN: 0272-1732 CODEN: IEMIDZ CCC: 0272-1732/95/$04.00 Language: English Treatment: Practical Abstract: New advanced architectures in DRAM interfaces seek to close the ever-widening performance gap between DRAM and microprocessor and to break the bandwidth bottleneck in graphics systems. We present an overview of five of these interfaces: EDO, SDRAM, RDRAM, CDRAM, and 3D-RAM. EDO will soon replace conventional DRAM, and SDRAM will partly take over in 66-MHz and higher frequency systems. Other interfaces will initially find target markets that exploit their unique features, and then seek wider market acceptance. Eventually, advances in DRAM will contribute to the trend toward a system on a chip. (11 Refs.) Classification: C5320G (Semiconductor storage); C5610S (System buses); C5610P (Peripheral interfaces) Thesaurus: DRAM chips; Peripheral interfaces; System buses Free Terms: DRAM interfaces; Performance gap; Graphics systems; EDO; SDRAM; RDRAM; CDRAM; 3D-RAM Item Availability: CD-ROM. INSPEC 5027113 B9510-0170J-007 Doc Type: Conference Paper Title: 3-D packaging-applications of vertical multichip modules (MCM-V) for microsystems Authors: Val, C. Affiliation: Thomson-CSF, Colombes, France Conf. Title: Sixteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Low-Cost Manufacturing Technologies for Tomorrow's Global Economy'. Proceedings 1994 IEMT Symposium (Cat. No.94CH3473-6) p. 387 vol.1 Publisher: IEEE New York, NY, USA Date: 1994 2 vol. (xii+404+viii+104 pp.) Country of Publication: USA ISBN: 0 7803 2037 9 CCC: 0 7803 2037 9/94/$3.00 Language: English Conf. Date: 12-14 Sept. 1994 Conf. Loc: La Jolla, CA, USA Conf. Sponsor: Electron. Ind. Assoc.; IEEE Components Packaging & Manuf. Technol. Soc Treatment: Application; Practical Abstract: Summary form only given. Classical 2-dimensional interconnection is compared to microtechniques using the 3rd dimension. Since 1989, several European projects with large companies including Alcatel, Daimler-Benz, Geo-Marconi, SGS Thomson, and several European universities, and Thomson-CSF have demonstrated, evaluated, and qualified the 3-D technique. The results of qualification are presented from 150 technology demonstrations plus 100 memory modules. The three-dimensional interconnection technology is presented for five application groups. (0 Refs.) Classification: B0170J (Product packaging); B2250 (Multichip modules) Thesaurus: Integrated circuit interconnections; Integrated circuit packaging; Multichip modules Free Terms: 3D packaging; Vertical multichip modules; MCM-V; Qualification; Memory modules; Technology demonstrations; Three-dimensional interconnection technology Item Availability: CD-ROM. INSPEC 4653790 B9406-2570-007 Doc Type: Journal Paper Title: Developing 3D memories Authors: Carson, J.C.; Suer, M.F.; Some, R.R. Affiliation: Irvine Sensors Corp., Costa Mesa, CA, USA Journal: IEEE Micro Vol: 13 Iss: 6 p. 6-7 Date: Dec. 1993 Country of Publication: USA ISSN: 0272-1732 CODEN: IEMIDZ Language: English Treatment: Practical Abstract: Two types of memory chip stacking technologies-full stack and short stack-are in the final stages of development. The full stack places up to 100 ICs in a 'loaf-of-bread' configuration. A typical full stack size is 2.5 cm*1.25 cm*0.65 cm. The short stack puts 4-16 ICs in a 'stack-of-pancakes' configuration. The resultant stack is similar to a thick IC, with typical dimensions of 1.25 cm*0.65 cm*0.025 cm. The two stack form factors support computer memory applications. While the full stack is typically interconnected to the next level of assembly by bump bonding to a substrate or wire bonding into a deep-drawn custom package, the short stack is designed for wirebonding into a deep-drawn custom package, the short stack is designed for wirebonding or TABing (tape automated bonding) into standard packages, SMT, or chip-on-board mounting. (0 Refs.) Classification: B2570 (Semiconductor integrated circuits); B0170J (Product packaging); B2240 (Microassembly techniques) Thesaurus: Integrated memory circuits; Lead bonding; Packaging Free Terms: 3D memories; Memory chip stacking technologies; ICs; Form factors; Computer memory; Substrate; Wire bonding; Tape automated bonding Item Availability: CD-ROM. INSPEC 4230306 B9210-0170J-033 Doc Type: Conference Paper Title: Hermetic plastic packages with applications to ruggedized boards Authors: Val, C.; Leroy, M.; Chambre, J.; Bourret, D.; Sempere, R.; Doucoure, A. Affiliation: Thomson CSF, Colombes, France Conf. Title: Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium (Cat. No.91CH3043-7) p. 356-60 Publisher: IEEE New York, NY, USA Date: 1991 xvi+449 pp. Country of Publication: USA ISBN: 0 7803 0155 2 CCC: CH3043-7/91/0000-0356$01.00 Language: English Conf. Date: 16-18 Sept. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: The feasibility of organic and inorganic deposition providing hermetic circuit boards has been demonstrated . The diffusion barrier is set up by depositing under plasma an inorganic layer instead of an organic layer. SiO/sub 2/ was chosen because it is easy to deposit and its properties are well-known. Three layers are necessary: conventional varnish (epoxy or acrylic) as a leveling-off agent, SiO/sub 2/ as a diffusion barrier, and parylene deposited under vacuum as a mechanical protective coating for the SiO/sub 2/. The board's hermetic protection is thus deposited in situ and is not obtained by means of a hermetic packaging. (20 Refs.) Classification: B0170J (Product packaging); B2210 (Printed circuits) Thesaurus: Packaging; Printed circuits; Protective coatings Free Terms: Organic deposition; Ruggedized boards; Inorganic deposition; Hermetic circuit boards; Diffusion barrier; Varnish; Leveling-off agent; Parylene; Mechanical protective coating; SiO/sub 2/ Chemical Index: SiO2/int O2/int Si/int O/int SiO2/bin O2/bin Si/bin O/bin Item Availability: CD-ROM. INSPEC 4067323 B9202-0170J-054 Doc Type: Conference Paper Title: The 3D interconnection-an enhanced densification approach with bare chips Authors: Val, C. Affiliation: Thomson-CSF, Colombes, France Conf. Title: 8th IEMT 1990. International Electronic Manufacturing Technology Symposium (Cat. No.90CH2833-2) p. 82-91 Publisher: IEEE New York, NY, USA Date: 1990 viii+515 pp. Country of Publication: USA CCC: CH2833-2/90/0000-0082$01.00 Language: English Conf. Date: 7-9 May 1990 Conf. Loc: Baveno, Italy Conf. Sponsor: IEEE Treatment: Practical Abstract: The author proposes interconnecting the bare chips along the Z axis rather than in the XY plane, thereby enabling a large enhancement of densification (by a factor of five to eight). This technique also substantially improves the high-frequency behavior of ICs. Inductances are very low, for example, since the longest conductor will not exceed 4.8 mm in length. In addition, the capacitances of the conductors, compared with those of the chips' silicon lateral areas, are 10 to 100 times less than they would be with an on-polyimide thin-film interconnection. An application consisting of a cube of eight stacked 256-kb SRAMs is presented. (6 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Integrated circuit technology; Modules; Packaging Free Terms: Inductance; Conductor capacitance; Multichip module; Stacked SRAMs; Cube packaging; 3D interconnection; Enhanced densification; Bare chips; High-frequency behavior Item Availability: CD-ROM. INSPEC 3897413 B91037007 Doc Type: Conference Paper Title: 3D interconnection for ultra-dense multichip modules Authors: Val, C.; Lemoine, T. Affiliation: Thomson-CSF, Colombes, France Conf. Title: 1990 Proceedings. 40th Electronic Components and Technology Conference (Cat. No.90CH2893-6) p. 540-7 vol.1 Publisher: IEEE New York, NY, USA Date: 1990 2 vol. xvi+1125 pp. Country of Publication: USA CCC: 0569-5503/90/0000-0540$01.00 Language: English Conf. Date: 20-23 May 1990 Conf. Loc: Las Vegas, NV, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: The increasing density of the interconnection of ASICs (application-specific integrated circuits) and memories is discussed. It is demonstrated that the interconnections of ASICs require the utilization of thin-film multilayers. However, since ASICs are interconnected in an extremely dense manner, the relative area occupied by the memories increases substantially, and currently amounts to approximately 50%. The 3-D interconnection technology allows reduction of the occupied area by a factor of 7 or 8 and thus yielded ultradense multichip modules. This interconnection approach consists of interconnecting the bare chips not in the xy plane but along the z axis. The interconnection process entails interconnecting the four sides of the cube formed by stacking n chips (n=8 by 10) on top of one another. To do so, the chips are individually interconnected on a thin film identical to a TAB (tape automated bonding) film by means of gold wires prior to cubing. This technique also substantially improves the high-frequency behavior of ICs. An application consisting of a cube of eight stacked 256-kb static random-access memories is being developed. (11 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); B1265D (Memory circuits) Thesaurus: Application specific integrated circuits; Modules; Packaging; SRAM chips; Tape automated bonding Free Terms: 3D interconnection; Ultra-dense multichip modules; ASICs; Thin-film multilayers; Memories; Bare chips; Interconnection process; Stacking; TAB; Cubing; High-frequency behavior; Static random-access memories Item Availability: CD-ROM. INSPEC 3848372 B91024029 Doc Type: Journal Paper Title: 3-D interconnection for ultra-dense multichip modules Authors: Val, C.; Lemoine, T. Affiliation: Thomson-CSF, Colombes, France Journal: IEEE Transactions on Components, Hybrids, and Manufacturing Technology Vol: 13 Iss: 4 p. 814-21 Date: Dec. 1990 Country of Publication: USA ISSN: 0148-6411 CODEN: ITTEDR CCC: 0148-6411/90/1200-0814$01.00 Language: English Treatment: New development; Practical; Experimental Abstract: A three-dimensional interconnection technology is described that allows a reduction of the occupied area by a factor of 7 or 8 as against 2-D interconnection. The approach consists of interconnecting the bare chips not in the XY plane, but along the Z-axis. The process entails interconnecting the four lateral areas (sides) of the cube formed by stacking n chips (n=8-10) on top of one another. The chips are individually interconnected on a thin film identical to a TAB (tape automatic bonded) film by means of gold wires, prior to cubing. These chips are standard, off-the-shelf, bump-free devices. After passing electrical testing and burn-in, they are then glued on top of one another with the TAB film. After these n chip+film assemblies have been cured (polymerized), a trim operation is carried out to cut the n-chips cube out of the TAB-film carrier cube. The trim line is approximately 100 mu m from the edge of the chips. The cube containing the n chips thus provides four lateral areas (sides) in which appear the cross sections of the gold wires connecting each lead of each chip to the corresponding leads on the flexible films. These gold wire cross-sections may be interconnected in two different ways according to the number of chip layouts/outputs or the conductor pitch. (10 Refs.) Classification: B2220J (Hybrid integrated circuits); B2240 (Microassembly techniques); B0170J (Product packaging) Thesaurus: Hybrid integrated circuits; Lead bonding; Modules; Packaging Free Terms: MCM; Of-the-shelf chips; Stacking bare chips; Vertical interconnection; Cube packaging; 3-D interconnection; Ultra-dense multichip modules; Three-dimensional interconnection technology; Z-axis; Bump-free devices; Glued on top of one another; TAB film; Trim operation; Au wire lead bonding Chemical Index: Au/el Item Availability: CD-ROM. INSPEC 4702636 B9408-1265B-027 C9408-5210-011 Doc Type: Journal Paper Title: Smart-substrate multichip-module systems Authors: Maly, W.; Feltham, D.B.I.; Gattiker, A.E.; Hobaugh, M.D.; Backus, K.; Thomas, M.E. Affiliation: Carnegie Mellon Univ., Pittsburgh, PA, USA Journal: IEEE Design & Test of Computers Vol: 11 Iss: 2 p. 64-73 Date: Summer 1994 Country of Publication: USA ISSN: 0740-7475 CODEN: IDTCEC CCC: 0740-7475/94/$4.00 Language: English Treatment: Practical Abstract: This implementation strategy enables incremental test of all system components, providing an alternative solution to the known good die testing problem. The authors present a simple microcontroller emulator designed and fabricated for study of the test logic needed as a key component of this method. (12 Refs.) Classification: B1265B (Logic circuits); B1265F (Microprocessors and microcomputers); C5210 (Logic design methods); C5120 (Logic and switching circuits) Thesaurus: Logic design; Logic testing; Multichip modules Free Terms: Multichip-module systems; Incremental test; Microcontroller emulator; Test logic; Smart-substrate Item Availability: CD-ROM. INSPEC 4677703 B9407-0170J-023 Doc Type: Conference Paper Title: Are there any alternatives to 'known good die' ? (MCMs) Authors: Gattiker, A.E.; Maly, W.; Thomas, M.E. Affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA Conf. Title: Proceedings 1994 IEEE Multi-Chip Module Conference MCMC-94 (Cat. No.93CH3396-9) p. 102-7 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 xi+149 pp. Country of Publication: USA ISBN: 0 8186 5560 7 CCC: 0 8186 5560 7/94/$03.00 Language: English Conf. Date: 15-17 March 1994 Conf. Loc: Santa Cruz, CA, USA Conf. Sponsor: IEEE Treatment: Economic/Commercial; Theoretical/Mathematical; Experimental Abstract: This paper presents a cost-based methodology for assessing the effectiveness of various MCM implementation strategies. It is focused on testing. Two approaches to the MCM testing problem are investigated in detail. One is based on the assumption that system components are perfect('known good die' approach) and the other uses the 'smart substrate' concept. An MCM using a smart substrate is one in which the substrate contains active circuitry for carrying out testing functions. For these two testing options, the obtained results suggest the existence of 'windows of opportunity' for both KGD and smart substrate solutions. (5 Refs.) Classification: B0170J (Product packaging); B0170E (Production facilities and engineering); B7210B (Automatic test and measurement systems) Thesaurus: Built-in self test; Costing; Economics; Integrated circuit manufacture; Integrated circuit testing; Multichip modules Free Terms: Known good die concept; MCM implementation strategies; Cost-based methodology; MCM testing; Smart substrate; Active circuitry; Cost model Item Availability: CD-ROM. INSPEC 4203853 B9209-2220J-009 Doc Type: Conference Paper Title: Monolithic VLSI vs. MCM a perspective on performance, yield, and manufacturing Authors: Siu, W.M. Affiliation: Intel Corp., Hillsboro, OR, USA Conf. Title: Proceedings. 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems (Cat. No.91TH0395-4) p. 116-19 Editors: Maly, W.; Walker, D.M. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 ix+301 pp. Country of Publication: USA ISBN: 0 8186 2457 4 CCC: 0 8186 2457 4/91$1.00 Language: English Conf. Date: 18-20 Nov. 1991 Conf. Loc: Hidden Valley, PA, USA Conf. Sponsor: IEEE Treatment: General/Review Abstract: MCMs are touted as the emerging challenge to monolithic VLSIs. The purported driving forces are performance and economics. While the potentials are attractive, many practical problems remain before MCMs become viable. Furthermore, it is not at clear that MCMs will replace monolithic VLSIs as suggested. The author contrasts these technologies. Using the implementation of a CPU function as an example, he examines the evolution of performance, yields, economics, of both the VLSI implementation and the MCM alternative. It is evident that, at the present time, the lack of a well-developed MCM technical and manufacturing infrastructure limits its penetration. An agenda to address these concerns will be presented. He concludes that MCM is an emerging technology that builds on the continued success of monolithic VLSIs and will augment rather than replace VLSIs. (0 Refs.) Classification: B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits) Thesaurus: Hybrid integrated circuits; VLSI Free Terms: Multichip modules; VLSI; Performance; Yield; Manufacturing; Economics; Monolithic VLSIs; CPU function; MCM Item Availability: CD-ROM. INSPEC 4203842 B9209-1265F-021 C9209-5440-013 Doc Type: Conference Paper Title: Wafer-scale massively parallel computing modules for fault-tolerant signal and data processing Authors: Lea, R.M. Affiliation: Aspex Microsyst. Ltd., Brunel Univ., Uxbridge, UK Conf. Title: Proceedings. 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems (Cat. No.91TH0395-4) p. 20-3 Editors: Maly, W.; Walker, D.M. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 ix+301 pp. Country of Publication: USA ISBN: 0 8186 2457 4 CCC: 0 8186 2457 4/91$1.00 Language: English Conf. Date: 18-20 Nov. 1991 Conf. Loc: Hidden Valley, PA, USA Conf. Sponsor: IEEE Treatment: General/Review Abstract: A WASP device is a WSI implementation of an ASP (Associative String Processor) substring and, as such, it constitutes a fundamental building block for the assembly of SIMD Massively Parallel Computer (MPC) components. This paper describes current progress in the WASP 3/4/5 programme. (4 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570 (Semiconductor integrated circuits); C5440 (Multiprocessing systems); C5130 (Microprocessor chips); C5135 (Digital signal processing chips); C5470 (Performance evaluation and testing); C5220P (Parallel architecture) Thesaurus: Digital signal processing chips; Fault tolerant computing; Microprocessor chips; Packaging; Parallel processing; VLSI Free Terms: WSI associative string processor; Fault tolerant processing; Signal processing; Massively parallel computing modules; Data processing; WASP device; WSI implementation; Fundamental building block; SIMD; Massively Parallel Computer; WASP 3/4/5 programme Item Availability: CD-ROM. INSPEC 4199259 B9209-1265F-009 C9209-5260B-024 Doc Type: Conference Paper Title: State-of-the-art of the wafer scale ELSA project Authors: Boubekeur, A.; Patry, J.-I.; Saucier, G.; Trilhe, J. Affiliation: INPG/CSI, Grenoble, France Conf. Title: Proceedings. 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems (Cat. No.91TH0395-4) p. 296-9 Editors: Maly, W.; Walker, D.M. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 ix+301 pp. Country of Publication: USA ISBN: 0 8186 2457 4 CCC: 0 8186 2457 4/91$1.00 Language: English Conf. Date: 18-20 Nov. 1991 Conf. Loc: Hidden Valley, PA, USA Conf. Sponsor: IEEE Treatment: General/Review Abstract: ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a whole wafer instead of implementing it in VLSI chips each containing a few processing elements. Potential advantages of wafer scale integration over conventional VLSI systems include lower power, higher speed and small volume. However, WSI suffers from low yield. Redundancy and reconfiguration techniques are used to enhance the overall yield. Both of these have been implemented in ELSA. Three software packages have been developed to completely (re)configure the wafer and build a working target array. (3 Refs.) Classification: B1265F (Microprocessors and microcomputers); B6140C (Optical information, image and video signal processing); B2570D (CMOS integrated circuits); C5260B (Computer vision and image processing techniques); C7410F (Communications computing); C5220P (Parallel architecture); C5440 (Multiprocessing systems); C5135 (Digital signal processing chips) Thesaurus: CMOS integrated circuits; Computerised picture processing; Digital signal processing chips; Parallel architectures; Redundancy; Systolic arrays; VLSI Free Terms: Yield enhancement; Redundancy; ELSA project; Massively parallel architectures; Low-level image processing; Regular architecture; Array processors; Wafer scale integration; WSI; Reconfiguration; Si wafer Chemical Index: Si/int Si/el Item Availability: CD-ROM. INSPEC 4184450 B9208-2570-031 Doc Type: Journal Paper Title: Prospects for WSI: a manufacturing perspective Authors: Maly, W. Affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA Journal: Computer Vol: 25 Iss: 4 p. 58-65 Date: April 1992 Country of Publication: USA ISSN: 0018-9162 CODEN: CPTRB4 CCC: 0018-9162/92/0400-0058$3.00 Language: English Treatment: Economic/Commercial Abstract: A manufacturing cost model that describes the relationships among characteristics of modern manufacturing processes, investment costs to achieve these characteristics, and basic IC parameters, including both die size and minimum feature size, is used to explain major trends in the past 20 yr of microelectronics. Results from this model indicate that it is not possible to continue progress in microelectronics through minimizing feature size, that the drive toward larger dies will gain momentum and lead gradually toward wafer-scale integration (WSI), and that manufacturing costs will keep WSI from becoming practical in the immediate future. Active-substrate flip-chip multichip modules (MCMs) are presented as an alternative that may provide both the performance gain and cost efficiency required. (10 Refs.) Classification: B2570 (Semiconductor integrated circuits); B0170J (Product packaging) Thesaurus: Integrated circuit manufacture; Modules; Packaging; VLSI Free Terms: WSI; Manufacturing cost model; Die size; Minimum feature size; Flip-chip multichip modules; Performance gain; Cost efficiency Item Availability: CD-ROM. INSPEC 5231793 B9605-1265Z-006 Doc Type: Conference Paper Title: A very-wide bandwidth digital VCO implemented in GaAs HBTs using frequency multiplication and division Authors: Campbell, P.M.; Greub, H.J.; Garg, A.; Steidl, S.; Maier, C.; Carlough, S.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 17th Annual Technical Digest 1995 (Cat. No.95CH35851) p. 311-14 Publisher: IEEE New York, NY, USA Date: 1995 xix+330 pp. Country of Publication: USA ISBN: 0 7803 2966 X CCC: 0 7803 2966 X/95/$4.00 Language: English Conf. Date: 29 Oct.-1 Nov. 1995 Conf. Loc: San Diego, CA, USA Conf. Sponsor: IEEE Electron Devices Soc.; IEEE Microwave Theory & Tech. Soc Treatment: Practical Abstract: A digital high-speed voltage-controlled oscillator (VCO) has been developed which uses frequency-multiplication and division to attain a wide frequency range of 0.5-13.66 GHz. The circuit is implemented in differential current-mode logic using GaAs-AlGaAs heterojunction bipolar transistors (HBTs). This paper discusses top-level system design as well as the design of several key components. (8 Refs.) Classification: B1265Z (Other digital circuits); B1230B (Oscillators); B2570B (Bipolar integrated circuits); B1350F (Solid-state microwave circuits and devices) Thesaurus: Aluminium compounds; Bipolar digital integrated circuits; Current-mode logic; Frequency dividers; Frequency multipliers; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductors; Microwave oscillators; Voltage-controlled oscillators Free Terms: Very-wide bandwidth VCO; Digital VCO; HBTs; Frequency multiplication; Frequency division; High-speed IC; Voltage-controlled oscillator; Differential current-mode logic; Top-level system design; Wideband operation; Broadband oscillator; CML; 0.5 To 13.66 GHz; GaAs-AlGaAs Numerical Index: Frequency 5.0E+08 to 1.366E+10 Hz Chemical Index: GaAs-AlGaAs/int AlGaAs/int GaAs/int Al/int As/int Ga/int AlGaAs/ss Al/ss As/ss Ga/ss GaAs/bin As/bin Ga/bin Item Availability: CD-ROM. INSPEC 5218690 B9605-1265F-011 C9605-5130-004 Doc Type: Conference Paper Title: Design verification and emulation of a multichip high-speed GaAs RISC processor using soft-programmable logic Authors: Carlough, S.; Steidl, S.; Airapetian, A.; Garg, A.; Maier, C.; Campbell, P.; Greub, H.J.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: Proceedings Eighth Annual IEEE International ASIC Conference and Exhibit (Cat. No.95TH8087) p. 164-6 Editors: Cook, W.A.; Hull, R.A.; Traver, C. Publisher: IEEE New York, NY, USA Date: 1995 xv+422 pp. Country of Publication: USA ISBN: 0 7803 2707 1 CCC: 0 7803 2707 1/95/$4.00 Language: English Conf. Date: 18-22 Sept. 1995 Conf. Loc: Austin, TX, USA Treatment: Practical Abstract: Soft-programmable logic is increasingly used to emulate and verify CMOS designs before fabrication. The F-RISC emulator uses this technology to emulate and verify a multichip GaAs RISC processor. An essential part of the F-RISC emulator is the mapping of the differential CML GaAs libraries to the Xilinx FPGA libraries. The emulator helped to detect several design errors. (2 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570B (Bipolar integrated circuits); B1130B (Computer-aided circuit analysis and design); C5130 (Microprocessor chips); C5220 (Computer architecture); C7410D (Electronic engineering computing); C5210B (Computer-aided logic design) Thesaurus: Bipolar digital integrated circuits; Circuit CAD; Current-mode logic; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductors; Integrated circuit design; Logic CAD; Microprocessor chips; Programmable logic devices; Reduced instruction set computing Free Terms: Design verification; RISC processor; Soft-programmable logic; HBT circuits; F-RISC emulator; Multichip processor; Differential CML libraries; Xilinx FPGA libraries; Design errors Item Availability: CD-ROM. INSPEC 5218664 B9605-1230B-011 Doc Type: Conference Paper Title: A high-bandwidth voltage controlled oscillator (VCO) with a frequency-multiplied/divided range of 0.25-20 GHz implemented in a GaAs HBT process Authors: Campbell, P.M.; Greub, H.J.; Garg, A.; Steidl, S.; Maier, C.; Carlough, S.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: Proceedings Eighth Annual IEEE International ASIC Conference and Exhibit (Cat. No.95TH8087) p. 49-52 Editors: Cook, W.A.; Hull, R.A.; Traver, C. Publisher: IEEE New York, NY, USA Date: 1995 xv+422 pp. Country of Publication: USA ISBN: 0 7803 2707 1 CCC: 0 7803 2707 1/95/$4.00 Language: English Conf. Date: 18-22 Sept. 1995 Conf. Loc: Austin, TX, USA Treatment: Practical Abstract: A high speed voltage-controlled oscillator (VCO) bas been developed using 50 GHz GaAs-AlGaAs HBTs which can generate differential signals in the range of 0.25-20 GHz. The design process was focused on producing a layout with highly-matched parasitic capacitance by exploiting the high degree of symmetry present in differential circuits. The system design and cell layout techniques are described in detail using examples from the VCO. The operation of the VCO is also discussed along with design tradeoffs. (2 Refs.) Classification: B1230B (Oscillators); B2570B (Bipolar integrated circuits); B1265Z (Other digital circuits) Thesaurus: Aluminium compounds; Application specific integrated circuits; Bipolar digital integrated circuits; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductors; Integrated circuit layout; Voltage-controlled oscillators Free Terms: High-bandwidth VCO; Voltage controlled oscillator; Frequency-multiplied/divided range; GaAs HBT process; High speed operation; Highly-matched parasitic capacitance; Differential circuits; Cell layout techniques; 0.25 To 20 GHz; GaAs-AlGaAs Numerical Index: Frequency 2.5E+08 to 2.0E+10 Hz Chemical Index: GaAs-AlGaAs/int AlGaAs/int GaAs/int Al/int As/int Ga/int AlGaAs/ss Al/ss As/ss Ga/ss GaAs/bin As/bin Ga/bin Item Availability: CD-ROM. INSPEC 5118447 B9601-0170J-007 C9601-5490-001 Doc Type: Conference Paper Title: Three dimensional stacking with diamond sheet heat extraction for subnanosecond machine design Authors: McDonald, J.F.; Greub, H.E.; Campbell, P.; Maier, C.; Garg, A.; Steidl, S. Affiliation: Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1995 Proceedings. Seventh Annual IEEE International Conference on Wafer Scale Integration (Cat. No.95CH3574-2) p. 62-71 Publisher: IEEE New York, NY, USA Date: 1995 ix+382 pp. Country of Publication: USA ISBN: 0 7803 2467 6 CCC: 0 7803 2466 8/95/$4.00 Language: English Conf. Date: 18-20 Jan. 1995 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Comput. Soc.; IEEE Components, Packaging, & Manuf. Technol. Soc Treatment: Practical Abstract: Devices are becoming available whose inherent switching speeds are approaching only a few picoseconds. CMOS FET devices with 0.12 micron channel length have exhibited f/sub T/ values of 89 GHz. SiGe HBTs have been demonstrated with an f/sub T/ of 117 GHz. InP/InGaAs/AlGaAs HBT's have exhibited an f/sub T/ of 200 GHz, with minimum feature sizes that are above one micron. InGaAs/AlGaAs MESFET's with 0.05 micron channel lengths have exhibited f/sub T/ values of 350 GHz. Clearly even faster devices are possible, and some have even begun to appear in viable fabrication lines where prospects for interesting levels of integration are being realized. For such technologies subnanosecond machine cycles seem possible. However, for conventional 2D chip or wafer fabrication some of the distances between key components on these substrates can be too long for subnanosecond operation. This may be true even for ideal transmission line interconnections that exhibit 'speed of light' propagation speeds and extremely wide bandwidths. At this point the last resort is to shorten these interconnections by rearranging the components in 3D structures, implying either die or wafer stacking. This paper explores some of the requirements for subnanosecond machine design, and practical schemes to accomplish this with discussion on how to distribute the power supply current and dissipate the heat generated. These schemes use the full array of WSI, WSHP and MCM technologies plus some new techniques for 3D vertical stacking. (0 Refs.) Classification: B0170J (Product packaging); B2570 (Semiconductor integrated circuits); C5490 (Other aspects of analogue and digital computers) Thesaurus: Cooling; Diamond; Heat sinks; Multichip modules; Wafer-scale integration Free Terms: Three dimensional stacking; Diamond sheet heat extraction; Subnanosecond machine design; CMOS FET devices; SiGe HBTs; InP/InGaAs/AlGaAs HBTs; InGaAs/AlGaAs MESFETs; Integration; Transmission line interconnections; Die stacking; Wafer stacking; Power supply current distribution; Vertical stacking; WSI; WSHP; MCM; Switching speeds; Fabrication; C Chemical Index: C/el Item Availability: CD-ROM. INSPEC 4938954 B9506-1265F-020 C9506-5130-013 Doc Type: Conference Paper Title: F-RISC/I: A 32 bit RISC processor implemented in GaAs HMESFET SBFL Authors: Tien, C.K.; Lewis, K.; Philhower, R.; Greub, H.J.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 15th Annual GaAs IC Symposium Technical Digest 1993 p. 145-8 Publisher: IEEE New York, NY, USA Date: Oct. 1993 xvii+382 pp. Country of Publication: USA ISBN: 0 7803 1393 3 CCC: 0-7803-1393-3/93/$3.00 Language: English Conf. Date: 10-13 Oct. 1993 Conf. Loc: San Jose, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 mu m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. Simulations have shown 400 MHz operation. The chip contains 92,340 transistors on a 7*7 mm/sup 2/ die and dissipates 3.8 W. The F-RISC/I processor exemplifies the CPU architecture, circuit design, and testing developed to fully take advantage of GaAs technology for high speed computing. (7 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570H (Other field effect integrated circuits); B1130B (Computer-aided circuit analysis and design); C5130 (Microprocessor chips); C5220 (Computer architecture); C7410D (Electronic engineering computing); C5210B (Computer-aided logic design) Thesaurus: Application specific integrated circuits; Carry logic; Circuit layout CAD; Computer architecture; Computer testing; Design for testability; Field effect logic circuits; Gallium arsenide; III-V semiconductors; Integrated circuit design; Integrated circuit testing; Logic CAD; Logic testing; MESFET integrated circuits; Reduced instruction set computing Free Terms: III-V semiconductor; Super-buffered FET logic; Harvard architecture; Testability; Level-sensitive scan design; Heterostructure MESFET; Datapath architecture; HMESFET SBFL; F-RISC/I; Reduced version; Fast RISC microprocessor; SBFL standard cell library; Design automation; CPU architecture; Circuit design; High speed computing; 32 Bit; 400 MHz; 3.8 W Numerical Index: Word length 3.2E+01 bit; Frequency 4.0E+08 Hz; Power 3.8E+00 W Item Availability: CD-ROM. INSPEC 4938939 B9506-1265F-019 C9506-5130-012 Doc Type: Conference Paper Title: A 500 ps 32 * 8 register file implemented in GaAs/AlGaAs HBTs (F-RISC/G processor) Authors: Nah, K.; Philhower, R.; Greub, H.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 15th Annual GaAs IC Symposium Technical Digest 1993 p. 71-4 Publisher: IEEE New York, NY, USA Date: Oct. 1993 xvii+382 pp. Country of Publication: USA ISBN: 0 7803 1393 3 CCC: 0-7803-1393-3/93/$3.00 Language: English Conf. Date: 10-13 Oct. 1993 Conf. Loc: San Jose, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A high speed register file has been designed that is well-suited for achieving the speed potential of a fast but yield-limited technology such as GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two linear feedback shift registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicate a read access time of 500 ps. (5 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570B (Bipolar integrated circuits); B1265B (Logic circuits); C5130 (Microprocessor chips); C5120 (Logic and switching circuits); C5220P (Parallel architecture); C7410D (Electronic engineering computing) Thesaurus: Aluminium compounds; Bipolar logic circuits; Boundary scan testing; Built-in self test; Computer testing; Current-mode logic; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductors; Integrated circuit testing; Shift registers Free Terms: III-V semiconductor; F-RISC/G processor; Current-mode logic; Address line driver; Sub-nanosecond circuits; HBT; Write circuit; Boundary scan scheme; Datapath chip; High speed register file; Yield-limited technology; Threshold voltage generator circuits; Test strategy; Linear feedback shift registers; Data patterns; Match circuit; Memory function; Read access time; 500 Ps; 32 Bit; GaAs-AlGaAs Numerical Index: Time 5.0E-10 s; Word length 3.2E+01 bit Chemical Index: GaAs-AlGaAs/int AlGaAs/int GaAs/int Al/int As/int Ga/int AlGaAs/ss Al/ss As/ss Ga/ss GaAs/bin As/bin Ga/bin Item Availability: CD-ROM. INSPEC 4898220 B9504-2250-046 Doc Type: Journal Paper Title: Development of a plastic encapsulated multichip technology for high volume, low cost commercial electronics Authors: Fillion, R.A.; Wojnarowski, R.J.; Gorcyzca, T.B.; Wildi, E.J.; Cole, H.S. Affiliation: Control Syst. & Electron. Technol., Gen. Electr. Corp. Res. & Dev. Center, Schenectady, NY, USA Journal: IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging Vol: 18 Iss: 1 p. 59-65 Date: Feb. 1995 Country of Publication: USA ISSN: 1070-9894 CODEN: IMTBE4 CCC: 1070-9894/95/$04.00 Language: English Treatment: Practical Abstract: Non-military/noncomputer electronics industry segments such as PC's, workstations, portable electronics, the automotive and medical industries, automated test equipment, and high-end consumer goods, are evolving rapidly. They demand higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weight, and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM, and COB. This paper describes an innovative embedded chip MCM technology that eliminates high cost structures, as well as materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper describes the thermal, mechanical, and chemical stability issues that drove this development, the process used to fabricate the modules, and the cost and yield advantages associated with this structure. (3 Refs.) Classification: B2250 (Multichip modules) Thesaurus: Encapsulation; Mechanical stability; Multichip modules; Thermal stability Free Terms: Plastic encapsulated multichip technology; Low cost commercial electronics; Embedded chip MCM technology; Epoxy encapsulant; MCM substrate; High volume production; High yield; Thermal stability; Mechanical stability; Chemical stability Item Availability: CD-ROM. INSPEC 4869155 B9503-2250-014 Doc Type: Conference Paper Title: Development of a plastic encapsulated multichip technology for high volume, low cost commercial electronics Authors: Fillion, R.; Wojnarowski, R.; Gorcyzca, T.; Wildi, E.; Cole, H. Affiliation: GE Corp. Res. & Dev., Schenectady, NY, USA Conf. Title: 1994 Proceedings. 44th Electronic Components and Technology Conference (Cat. No.94CH3241-7) p. 805-9 Publisher: IEEE New York, NY, USA Date: 1994 xvii+1118 pp. Country of Publication: USA ISBN: 0 7803 0914 6 CCC: 0569-5503/94/0000-0805$3.00 Language: English Conf. Date: 1-4 May 1994 Conf. Loc: Washington, DC, USA Conf. Sponsor: IEEE Components Hybrids & Manuf. Technol. Soc.; Electron. Ind. Assoc Treatment: Practical; Experimental Abstract: Non-military/non-computer electronics industry segments such as PCs, workstations, portable electronics, automotive, medical, automated test equipment and high end consumer, are evolving to higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weigh and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM and COB. This paper describes the development of an innovative embedded chip MCM technology that eliminates high cost structures, materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper describes the thermal, mechanical and chemical stability issues that drove this development, the process used to fabricate the modules and the cost and yield advantages associated with this structure. (3 Refs.) Classification: B2250 (Multichip modules); B2240 (Microassembly techniques) Thesaurus: Encapsulation; Integrated circuit manufacture; Microassembling; Multichip modules; Plastic packaging; Stability Free Terms: Plastic encapsulated multichip technology; Low cost commercial electronics; Embedded chip MCM technology; Epoxy encapsulant; High volume production; High yield; Thermal stability; Mechanical stability; Chemical stability; Module fabrication Item Availability: CD-ROM. INSPEC 4801141 B9412-2220J-012 C9412-5130-015 Doc Type: Conference Paper Title: Thermal design of an advanced multichip module for a RISC processor Authors: Garg, A.; Sham, T.-L.; Greub, H.; Loy, J.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.94CH35712) p. 608-11 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1994 xvii+639 pp. Country of Publication: USA ISBN: 0 8186 6565 3 CCC: 1063-6404/94/$4.00 Language: English Conf. Date: 10-12 Oct. 1994 Conf. Loc: Cambridge, MA, USA Conf. Sponsor: IEEE Comput. Soc.; IEEE Circuits & Syst. Soc.; IEEE Electron Devices Soc Treatment: Application; Practical Abstract: Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a 1-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology and triple-level full-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (<or=10 GHz) and high-density (<or=40 mu m pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2.0*10/sup 5/ W/m/sup 2/. Poor heat conduction ability of GaAs chips make it tough to dissipate this hear. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented. (10 Refs.) Classification: B2220J (Hybrid integrated circuits); B1265B (Logic circuits); B2570B (Bipolar integrated circuits); B0170J (Product packaging); B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5120 (Logic and switching circuits) Thesaurus: Bipolar integrated circuits; Emitter-coupled logic; Heterojunction bipolar transistors; Integrated circuit technology; Microprocessor chips; Multichip modules; Reduced instruction set computing Free Terms: Thermal design; Multichip module; RISC processor; High-speed interchip connections; Package; Circuit applications; AlGaAs/GaAs heterojunction bipolar transistor technology; Triple-level full-differential current mode logic; Power consumption; Integration level; Heat flux; Heat conduction; GaAs chips; Thermal stability; Multilayer substrate; Parylene; Low dielectric constant insulator; Fine pitch copper; Thermal simulation; 250 W; 1 Ns; 32 Bit; 50 GHz; 10 GHz; 40 Micron; AlGaAs-GaAs; Cu Numerical Index: Power 2.5E+02 W; Time 1.0E-09 s; Word length 3.2E+01 bit; Frequency 5.0E+10 Hz; Bandwidth 1.0E+10 Hz; Size 4.0E-05 m Chemical Index: AlGaAs-GaAs/int AlGaAs/int GaAs/int Al/int As/int Ga/int AlGaAs/ss Al/ss As/ss Ga/ss GaAs/bin As/bin Ga/bin; Cu/el Item Availability: CD-ROM. INSPEC 4677655 B9407-1265F-015 C9407-5130-005 Doc Type: Conference Paper Title: Design of a package for a high-speed processor made with yield-limited technology Authors: Garg, A.; Loy, J.; Greub, H.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: Proceedings. Fourth Great Lakes Symposium on VLSI. Design Automation of High Performance VLSI Systems GLSV '94 (Cat. No.94TH0603-1) p. 110-13 Publisher: IEEE Comput. Soc. Press Los Almitos, CA, USA Date: 1994 xiv+258 pp. Country of Publication: USA ISBN: 0 8186 5610 7 CCC: 1066-1395/94/$3.00 Language: English Conf. Date: 4-5 March 1994 Conf. Loc: Notre Dame, IN, USA Conf. Sponsor: IEEE; Univ. Notre Dame; ACM Treatment: Practical Abstract: The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database. (7 Refs.) Classification: B1265F (Microprocessors and microcomputers); B0170J (Product packaging); B2570B (Bipolar integrated circuits); C5130 (Microprocessor chips); C5220 (Computer architecture) Thesaurus: Bipolar integrated circuits; Emitter-coupled logic; Microprocessor chips; Multichip modules; Reduced instruction set computing Free Terms: High-speed processor; Yield-limited technology; High density thin film multichip module; Fast Reduced Instruction Set Computer; F-RISC/G; Heterojunction bipolar transistor technology; Thermomechanical constraints; Electrical constraints; Thermal constraints; 1 Ns Numerical Index: Time 1.0E-09 s Item Availability: CD-ROM. INSPEC 4609203 B9404-0170J-003 Doc Type: Journal Paper Title: Frequency domain (1 kHz-40 GHz) characterisation of thin films for multichip module packaging technology Authors: Liu, W.-T.; Cochrane, S.; Wu, X.-M.; Singh, P.K.; Zhang, X.; Knorr, D.B.; McDonald, J.F.; Rymaszewski, E.J.; Borrego, J.M.; Lu, T.-M. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Journal: Electronics Letters Vol: 30 Iss: 2 p. 117-18 Date: 20 Jan. 1994 Country of Publication: UK ISSN: 0013-5194 CODEN: ELLEAK CCC: 0013-5194/94/$7.50+0.00 Language: English Treatment: Experimental Abstract: Parallel plate capacitors for the broadband dielectric characterisation of both high (amorphous BaTiO/sub 3/ and amorphous TaO/sub x/) and low (parylene) dielectric constant thin films were fabricated at low temperature (<200 degrees C). The dielectric constant and loss tangent were determined through the measurement of C, G and the S parameters of the capacitors. These thin film dielectrics exhibit no dispersion in the frequency range 1 kHz-40 GHz. (7 Refs.) Classification: B0170J (Product packaging); B2220E (Thin film circuits); B2220J (Hybrid integrated circuits); B2810 (Dielectric materials and properties); B0560 (Polymers and plastics (engineering materials science)) Thesaurus: Amorphous state; Barium compounds; Dielectric losses; Dielectric thin films; Multichip modules; Permittivity; Polymer films; S-parameters; Tantalum compounds; Thin film capacitors Free Terms: Frequency domain characterisation; Multichip module packaging technology; Parallel plate capacitors; Broadband dielectric characterisation; High permittivity; Amorphous BaTiO/sub 3/; Amorphous TaO/sub x/; Low permittivity; Parylene; Dielectric constant; Dielectric thin films; Loss tangent; S-parameters; Thin film dielectrics; 1 KHz-40 GHz; MCM; 200 C; 1 KHz to 40 GHz; BaTiO/sub 3/; TaO Numerical Index: Temperature 4.73E+02 K; Frequency 1.0E+03 to 4.0E+10 Hz Chemical Index: BaTiO3/int TiO3/int Ba/int O3/int Ti/int O/int BaTiO3/ss TiO3/ss Ba/ss O3/ss Ti/ss O/ss; TaO/int Ta/int O/int TaO/bin Ta/bin O/bin Item Availability: CD-ROM. INSPEC 4503597 B9311-2570-034 Doc Type: Conference Paper Title: Use of high dielectric constant insulators for bypass capacitance in WSI and wafer scale hybrid multichip modules Authors: Philhower, R.; Van Etten, J.; Nah, K.S.; Loy, C.J.; Maier, C.; Campbell, P.; Grueb, H.J.; Li, P.; Liu, W.-T.; Lu, T.-M.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 318-28 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Theoretical/Mathematical; Experimental Abstract: The exceptionally large amounts of bypass-capacitance requirements of wafer scale integration (WSI) and wafer scale hybrid packaging/multichip module (WSHP/MCM) based systems operating at state-of-the-art switching speeds are explored. The capacitance required may become considerably larger than can be obtained by simply making thin-oxide-metal-plate capacitors unless alternate design styles which exhibit less switching noise are adopted for the circuits employed. Some of the criteria for picking the value of the bypass capacitance are examined, together with techniques for introducing high-dielectric-constant materials into the processing of the semiconductor substrates. The possibility of depositing thin layers of amorphous BaTiO/sub 3/ at low temperature to form a reliable, pin-hole free dielectric for bypass capacitance by use of ionized cluster beam techniques is explored. Deposition of the amorphous material on both metal and semiconductor substrates is possible. (9 Refs.) Classification: B2570 (Semiconductor integrated circuits); B2220J (Hybrid integrated circuits); B0170J (Product packaging); B2220E (Thin film circuits) Thesaurus: Capacitance; Hybrid integrated circuits; Insulating thin films; Integrated circuit technology; Multichip modules; Packaging; Thin film capacitors; VLSI Free Terms: Wafer scale hybrid MCM; Metal substrates; Thin film deposition; High dielectric constant insulators; Bypass capacitance; WSI; Multichip modules; Wafer scale integration; Packaging; Switching noise; Semiconductor substrates; Pin-hole free dielectric; Ionized cluster beam techniques; Amorphous BaTiO/sub 3/ Chemical Index: BaTiO3/int TiO3/int Ba/int O3/int Ti/int O/int BaTiO3/ss TiO3/ss Ba/ss O3/ss Ti/ss O/ss Item Availability: CD-ROM. INSPEC 4503596 B9311-0170J-018 Doc Type: Conference Paper Title: Three dimensional hybrid wafer scale integration using the GE high density interconnect technology Authors: Wojnarowski, R.J.; Fillion, R.A.; Gorowitz, B.; Saia, R. Affiliation: Gen. Electr. Co., Schenectady, NY, USA Conf. Title: 1993 Proceedings. Fifth Annual IEEE International Conference on Wafer Scale Integration (Cat. No.93CH3227-6) p. 309-17 Publisher: IEEE New York, NY, USA Date: 1993 ix+374 pp. Country of Publication: USA ISBN: 0 7803 0867 0 CCC: 0 7803 0867 0/93/$3.00 Language: English Conf. Date: 20-22 Jan. 1993 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A three-dimensional multichip technology is discussed. It provides solutions to the interconnect and packaging problems associated with very high density requirements of large distributed processing systems and large solid-state memory systems. The technical approach involves an extension of the 2D multichip module (MCM) circuits fabricated with the high-density-interconnect (HDI) overlay technology. These are then stacked and interconnected with a modified version of the 2D HDI interconnect process applied to the side edges of the stack. Test structures and a stack of function circuit circuits are fabricated and tested. The features of this approach, a description of the process, and the results of tests on the demonstration vehicles are presented. (6 Refs.) Classification: B0170J (Product packaging); B2220J (Hybrid integrated circuits) Thesaurus: Hybrid integrated circuits; Integrated circuit technology; Multichip modules; VLSI Free Terms: 3D hybrid WSI; HDI overlay technology; 3D MCM; Wafer scale integration; High density interconnect technology; Three-dimensional multichip technology; Interconnect; Packaging; Very high density requirements; Large distributed processing systems; Solid-state memory systems; Multichip module Item Availability: CD-ROM. INSPEC 4260010 B9211-2220J-029 Doc Type: Conference Paper Title: Wideband wafer-scale interconnections in a wafer scale hybrid package for a 1000 MIPS highly pipelined GaAs/AlGaAs HBT RISC Authors: Philhower, R.; Van Etten, J.S.; Dabral, S.; Nah, K.; Greub, H.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: Proceedings. International Conference on Wafer Scale Integration (Cat. No.92CH3088-2) p. 145-54 Editors: Jain, V.K.; Wyatt, P.W. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1992 xi+363 pp. Country of Publication: USA ISBN: 0 8186 2482 5 CCC: 0 8186 2482 5/92$01.00 Language: English Conf. Date: 22-24 Jan. 1992 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: A wideband thin-film wafer scale hybrid package (WSHP) or multi-chip module (MCM) will be used to interconnect the chips of a high-performance RISC (reduced instruction set computer) architecture developed at Rensselaer. This architecture is being implemented using GaAs/AlGaAs heterojunction bipolar transistors (HBTs) and triple-level differential current-mode logic. Because of high power consumption yield limitations of the HBT technology, the processor is partitioned into multiple chips. These chips must be connected using lines capable of handling the fast rise-time signals. Also, the MCM must contain integrated bypass capacitors and termination resistors. (12 Refs.) Classification: B2220J (Hybrid integrated circuits); B2570B (Bipolar integrated circuits); B1265F (Microprocessors and microcomputers); B2220E (Thin film circuits); B0170J (Product packaging); B2550F (Metallisation and interconnection technology) Thesaurus: Aluminium compounds; Bipolar integrated circuits; Gallium arsenide; Heterojunction bipolar transistors; Hybrid integrated circuits; III-V semiconductors; Metallisation; Packaging; Pipeline processing; Reduced instruction set computing; Thin film circuits; VLSI Free Terms: Semiconductor; Multichip modules; Wideband interconnects; Flip chips; Wafer-scale interconnections; Wafer scale hybrid package; RISC; WSHP; Multi-chip module; MCM; Reduced instruction set computer; Heterojunction bipolar transistors; HBTs; Triple-level differential current-mode logic; Power consumption; Yield limitations; HBT technology; Multiple chips; Fast rise-time signals; Integrated bypass capacitors; Termination resistors; 1000 MIPS; GaAs-AlGaAs Numerical Index: Computer execution rate 1.0E+09 IPS Chemical Index: GaAs-AlGaAs/int AlGaAs/int GaAs/int Al/int As/int Ga/int AlGaAs/ss Al/ss As/ss Ga/ss GaAs/bin As/bin Ga/bin Item Availability: CD-ROM. INSPEC 4194305 B9208-1265F-063 C9208-5135-018 Doc Type: Conference Paper Title: A 36-chip multiprocessor multichip module made with the General Electric high density interconnect technology Authors: Gdula, M.; Welles, K.B., II; Wojnarowski, R.J.; Neugebauer, C.A.; Burgess, J.F. Affiliation: General Electric Corp. Res. & Dev. Center, Schenectady, NY, USA Conf. Title: 1991 Proceedings. 41st Electronic Components and Technology Conference (Cat. No.91CH2989-2) p. 727-30 Publisher: IEEE New York, NY, USA Date: 1991 xvi+901 pp. Country of Publication: USA ISBN: 0 7803 0012 2 CCC: 0569-5503/91/0000-0727$01.00 Language: English Conf. Date: 11-16 May 1991 Conf. Loc: Atlanta, GA, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: A unique packaging and interconnect technology was used to build a multichip, four-CPU-element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed circuit board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz. (37 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2220J (Hybrid integrated circuits); B0170J (Product packaging); C5135 (Digital signal processing chips); C5220P (Parallel architecture) Thesaurus: Digital signal processing chips; Hybrid integrated circuits; Modules; Packaging; Parallel architectures Free Terms: Multiprocessor multichip module; General Electric high density interconnect technology; Packaging; Pipeline parallel processing computer module; Texas Instruments; TMS320C25; Digital signal processors; Area; Interconnect capacitance; Clocking Item Availability: CD-ROM. INSPEC 4127983 B9205-1265F-025 C9205-5130-018 Doc Type: Conference Paper Title: F-RISC/G: AlGaAs/GaAs HBT standard cell library Authors: Nah, K.; Philhower, R.; Van Etten, J.S.; Simmons, S.; Tsinker, V.; Loy, J.; Greub, H.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3) p. 297-300 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xvi+654 pp. Country of Publication: USA ISBN: 0 8186 2270 9 CCC: CH3040-3/91/0000-0297$01.00 Language: English Conf. Date: 14-16 Oct. 1991 Conf. Loc: Cambridge, MA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps. (4 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570B (Bipolar integrated circuits); B2560J (Bipolar transistors); C5130 (Microprocessor chips); C5220 (Computer architecture) Thesaurus: Aluminium compounds; Bipolar integrated circuits; Gallium arsenide; Heterojunction bipolar transistors; III-V semiconductors; Microprocessor chips; Reduced instruction set computing Free Terms: Differential current mode logic; F-RISC/G; Standard cell library; Fast reduced instruction set computer; AlGaAs/GaAs heterojunction bipolar transistor; Instruction cycle time; Unloaded gate delays; 1 Ns; AlGaAs-GaAs Numerical Index: Time 1.0E-09 s Chemical Index: AlGaAs-GaAs/int AlGaAs/int GaAs/int Al/int As/int Ga/int AlGaAs/ss Al/ss As/ss Ga/ss GaAs/bin As/bin Ga/bin Item Availability: CD-ROM. INSPEC 4127982 B9205-1265F-024 C9205-5130-017 Doc Type: Conference Paper Title: F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation Authors: Tien, C.K.; Poon, C.C.; Greub, H.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3) p. 293-6 Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xvi+654 pp. Country of Publication: USA ISBN: 0 8186 2270 9 CCC: CH3040-3/91/0000-0293$01.00 Language: English Conf. Date: 14-16 Oct. 1991 Conf. Loc: Cambridge, MA, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed. The GaAs technology environment is investigated and compared to that of Si. (15 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570H (Other field effect integrated circuits); C5130 (Microprocessor chips); C5220 (Computer architecture) Thesaurus: Field effect integrated circuits; Gallium arsenide; III-V semiconductors; Microprocessor chips; Reduced instruction set computing; VLSI Free Terms: F-RISC/I; Fast reduced instruction set computer; MESFET; Microprocessor; SBFL standard cells; System architecture; CPU architecture; Circuit level optimization; Implementation; Performance; 400 MHz; GaAs Numerical Index: Frequency 4.0E+08 Hz Chemical Index: GaAs/int As/int Ga/int GaAs/bin As/bin Ga/bin Item Availability: CD-ROM. INSPEC 4076744 B9203-2570-017 C9203-7410D-019 Doc Type: Conference Paper Title: A fast router and placement algorithm for wafer scale integration and wafer scale hybrid packaging Authors: McDonald, J.F.; Donlan, B.J.; Russinovich, M.E.; Philhower, R.; Nah, K.S.; Greub, H. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9) p. 331-40 Editors: Little, M.J.; Jain, V.K. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9126 3 Language: English Conf. Date: 29-31 Jan. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: The authors describe an algorithm developed for discretionary wafer routing needed for wafer scale integration (WSI) or multichip packaging. A very fast multilayer line probe router has been developed and implemented. The router uses a collection of depth-first heuristics to provide an extremely fast route with exceptional wiring quality and very high completion rate. The search algorithms and data structures are significantly different from those of D. Hightower (1969). These differences make it possible to route the special kinds of wiring needed for WSI in under a minute of VAX 6410 CPU time in many cases. Such a high-speed router will be necessary when line routing is to proceed at wafer throughput rates for fabrication. (20 Refs.) Classification: B2570 (Semiconductor integrated circuits); B2220J (Hybrid integrated circuits); B1130B (Computer-aided circuit analysis and design); C7410D (Electronic engineering computing) Thesaurus: Circuit layout CAD; Hybrid integrated circuits; VLSI Free Terms: Fast router and placement algorithm; Wafer scale integration; Wafer scale hybrid packaging; Discretionary wafer routing; Multichip packaging; Multilayer line probe router; Depth-first heuristics; High completion rate; VAX 6410; High-speed router Item Availability: CD-ROM. INSPEC 4076729 B9203-2570-011 Doc Type: Conference Paper Title: An overview and analysis of 3D WSI Authors: McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9) p. 223-35 Editors: Little, M.J.; Jain, V.K. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9126 3 Language: English Conf. Date: 29-31 Jan. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: General/Review; Theoretical/Mathematical Abstract: The author reviews the early trends in 3-D WSI (wafer scale integration) and examines recent breakthroughs in technology to assess the viability of 3-D. It is concluded that this option is rich with possibility for the designer. However, not every architecture can benefit equally from this packaging approach. An attempt is made to quantify this impact by computing an average wire-shortening effect from 3-D partitioning, but even this average improvement is pessimistic if the given architecture is such that the most critical paths can all be placed on the vertical wiring runs in the stack, depending on the vertical spacing of the wafers. (13 Refs.) Classification: B2570 (Semiconductor integrated circuits); B1265F (Microprocessors and microcomputers); B0170J (Product packaging); B2220J (Hybrid integrated circuits) Thesaurus: Hybrid integrated circuits; Microprocessor chips; Packaging; VLSI Free Terms: WSI stacking; Overview; Analysis; 3D WSI; Wafer scale integration; Breakthroughs in technology; Viability of 3-D; Average wire-shortening effect; 3-D partitioning; Critical paths; Vertical wiring runs; Vertical spacing Item Availability: CD-ROM. INSPEC 4076725 B9203-1265F-034 C9203-5440-008 Doc Type: Conference Paper Title: An 80 MHz digital signal processing multichip module made with the General Electric high density interconnect technology Authors: Gdula, M.; Welles, K.B., II; Wojnarowski, R.J. Affiliation: GE Corp. Res. & Dev. Center, Schenectady, NY, USA Conf. Title: 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9) p. 192-8 Editors: Little, M.J.; Jain, V.K. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1991 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9126 3 Language: English Conf. Date: 29-31 Jan. 1991 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: New development; Practical; Experimental Abstract: A unique packaging and interconnect technology was used to build a multichip, four CPU element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed-circuit-board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz. (0 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2570D (CMOS integrated circuits); B2220J (Hybrid integrated circuits); B0170J (Product packaging); C5440 (Multiprocessing systems); C5220P (Parallel architecture) Thesaurus: CMOS integrated circuits; Digital signal processing chips; Hybrid integrated circuits; Packaging; Parallel machines; Pipeline processing Free Terms: Interconnect capacitance reduction; Package parasitics elimination; Clock frequency 90 MHz; MCM; DSP chips; CMOS; HDI; Multichip module; General Electric; High density interconnect technology; Four CPU element; Pipeline parallel processing computer module; TMS320C25; Digital signal processors; Reduction in area; 40 To 90 MHz Numerical Index: Frequency 4.0E+07 to 9.0E+07 Hz Item Availability: CD-ROM. INSPEC 4023967 B91076946 Doc Type: Conference Paper Title: Chromium as an adhesion promoter/diffusion barrier for Cu on parylene Authors: Dabral, S.; Yang, G.-R.; Bakhru, H.; Lu, T.-M.; McDonald, J.F. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1991 Proceedings. Eighth International IEEE VLSI Multilevel Interconnection Conference (Cat. No.91TH0359-0) p. 408-10 Publisher: IEEE New York, NY, USA Date: 1991 456 pp. Country of Publication: USA ISBN: 0 87942 673 X CCC: TH0359-0/91/0000-0408$01.00 Language: English Conf. Date: 11-12 June 1991 Conf. Loc: Santa Clara, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: The low dielectric constant of parylene-n (PA-n) and high conductivity of Cu can provide a low RC time constant interconnection scheme. Vapor deposited PA-n and Partially Ionized Beam (PIB) deposited Cu have been employed for this study. Both Cu and Cr formed plasmas during the PIB deposition. The diffusion of Cu in low concentrations into PA-n at temperatures higher than 350 degrees C has been previously observed. Another problem with high temperature anneals (>300 degrees C) in the Cu/PA-n system is the gradual loss of adhesion. Here, chromium has been demonstrated as a diffusion barrier and adhesion promoter. Previous studies of different systems have used Cr with mixed success as a diffusion barrier. Thus, it is essential to determine its efficiency in the specific Cu/Cr/PA-n system. In this system, thin Cr layers, 1000-100 AA, served as a good barrier and adhesion promoter up to the tested temperature of 350 degrees C. These thin layers are essential to minimize the resistive contribution due to skin effect at high frequencies. (4 Refs.) Classification: B2550F (Metallisation and interconnection technology); B2570 (Semiconductor integrated circuits); B0170N (Reliability); B0560 (Polymers and plastics (engineering materials science)); B0530 (Metals and alloys (engineering materials science)) Thesaurus: Chromium; Copper; Metallisation; Polymer films; Reliability; VLSI Free Terms: VLSI; Multilevel interconnection; Reliability issues; Parylene; Low dielectric constant; High conductivity; Low RC time constant interconnection scheme; Diffusion barrier; Adhesion promoter; Tested temperature; 300 To 350 C; 1000 To 100 AA; Thin Cr layers; Si Numerical Index: Temperature 5.73E+02 to 6.23E+02 K; Size 1.0E-08 to 1.0E-07 m Chemical Index: Cr/int Cu/int Si/int Cr/el Cu/el Si/el; Si/sur Si/el; Cr/int Cr/el Item Availability: CD-ROM. INSPEC 3948572 B91055105 C91052477 Doc Type: Journal Paper Title: High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic Authors: Greub, H.J.; McDonald, J.F.; Creedon, T.; Yamaguchi, T. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Journal: IEEE Journal of Solid-State Circuits Vol: 26 Iss: 5 p. 749-62 Date: May 1991 Country of Publication: USA ISSN: 0018-9200 CODEN: IJSCBC CCC: 0018-9200/91/0500-0749$01.00 Language: English Treatment: Practical Abstract: A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 mu m*2.4 mu m and a maximum f/sub t/ of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees. (17 Refs.) Classification: B1265B (Logic circuits); B1130B (Computer-aided circuit analysis and design); B2570B (Bipolar integrated circuits); C5210B (Computer-aided logic design); C7410D (Electronic engineering computing) Thesaurus: Bipolar integrated circuits; Circuit analysis computing; Integrated logic circuits; Logic CAD Free Terms: CAD; Arithmetic/logic unit; Standard cell library; Modeling technique; Current tree logic; Tektronix advanced bipolar process; GST1; Fast reduced instruction set computer; FRISC; High-speed differential logic; Gate propagation delays; Power dissipation; ALU; Transient behavior; 32 Bit; 90 Ps; 68 Ps; 10 MW; 15.5 GHz; 250 MIPS Numerical Index: Word length 3.2E+01 bit; Time 9.0E-11 s; Time 6.8E-11 s; Power 1.0E-02 W; Frequency 1.55E+10 Hz; Computer execution rate 2.5E+08 IPS Item Availability: CD-ROM. INSPEC 3898371 B91038556 Doc Type: Conference Paper Title: Copper-parylene interactions in multilevel interconnection structures Authors: McDonald, J.F.; Dabral, S.; Yang, G.-R.; Bakhru, H.; Lu, T.-M. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1990 Proceedings. Seventh International IEEE VLSI Multilevel Interconnection Conference (Cat. No.90TH0325-1) p. 345-7 Publisher: IEEE New York, NY, USA Date: 1990 494 pp. Country of Publication: USA CCC: TH-0325-1/90/0000-0345$01.00 Language: English Conf. Date: 12-13 June 1990 Conf. Loc: Santa Clara, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: Copper is investigated as an interconnect metal and parylene as the interlayer dielectric. It has been found that copper adheres to the parylene well. The effect of a soldering step has been simulated by annealing. Using Rutherford backscattering (RBS) and secondary ion mass spectroscopy (SIMS) it has been found that copper does indeed diffuse into the parylene at elevated temperatures. However, this diffusion is small and does not affect the dielectric leakage properties much. (9 Refs.) Classification: B2550F (Metallisation and interconnection technology) Thesaurus: Annealing; Chemical interdiffusion; Copper; Dielectric thin films; Metallisation; Rutherford backscattering; Secondary ion mass spectroscopy Free Terms: Multilevel interconnection structures; Interconnect metal; Parylene; Interlayer dielectric; Soldering step; Annealing; Rutherford backscattering; Secondary ion mass spectroscopy; Dielectric leakage properties; Cu Chemical Index: Cu/int Cu/el Item Availability: CD-ROM. INSPEC 3897415 B91038917 Doc Type: Conference Paper Title: Bare chip test techniques for multichip modules Authors: Fillion, R.A.; Wojnarowski, R.J.; Daum, W. Affiliation: GE Corporate Res. & Dev. Center, Schenectady, NY, USA Conf. Title: 1990 Proceedings. 40th Electronic Components and Technology Conference (Cat. No.90CH2893-6) p. 554-8 vol.1 Publisher: IEEE New York, NY, USA Date: 1990 2 vol. xvi+1125 pp. Country of Publication: USA CCC: 0569-5503/90/0000-0554$01.00 Language: English Conf. Date: 20-23 May 1990 Conf. Loc: Las Vegas, NV, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: Practical Abstract: A unique bare-chip test methodology has been developed based upon the GE high-density interconnect (HDI) technology. This methodology allows at-speed testing and screening of complex ASICs (application-specific integrated circuits) and microprocessor chips over the full military temperature range in standard chip-carrier test sockets without any special fixturing or probe cards or in clusters of common chips in a test array. The authors describe the HDI packaging approach and how it is being utilized to perform bare-ship pretest of RAM chips, processors, and complex ASICs and how it can be utilized to provide full preassembly burn-in. (0 Refs.) Classification: B2570 (Semiconductor integrated circuits); B1265F (Microprocessors and microcomputers); B1265D (Memory circuits) Thesaurus: Application specific integrated circuits; Integrated circuit testing; Integrated memory circuits; Microprocessor chips; Modules; Random-access storage Free Terms: Multichip modules; Bare-chip test methodology; GE high-density interconnect; At-speed testing; Screening; Complex ASICs; Microprocessor chips; Military temperature range; Standard chip-carrier test sockets; Clusters; Bare-ship pretest; RAM chips; Preassembly burn-in Item Availability: CD-ROM. INSPEC 3763931 B90076274 Doc Type: Conference Paper Title: Wafer scale integration (WSI) of programmable gate arrays (PGA's) Authors: McDonald, J.F.; Dabral, S.; Philhower, R.; Russinovich, M.E. Affiliation: Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA Conf. Title: 1990 Proceedings. International Conference on Wafer Scale Integration (Cat. No.90CH2814-2) p. 329-38 Editors: Brewer, J.; Little, M.J. Publisher: IEEE Comput. Soc. Press Los Alamitos, CA, USA Date: 1990 xiv+342 pp. Country of Publication: USA ISBN: 0 8186 9013 5 CCC: CH2814-2/90/0000-0329$01.00 Language: English Conf. Date: 23-25 Jan. 1990 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: New development; Practical Abstract: Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM's. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is the same on all wafers. What one would like is a similar approach which could be applied to logic circuits. Traditionally, however, logic is viewed as being inherently less regular than memory. This paper addresses one approach to accomplishing WSI based on a highly regular, restructurable logic component known as Programmable Gate Array (PGA), which is also known as a Logic Component Array (LCA). (8 Refs.) Classification: B2570 (Semiconductor integrated circuits); B1265B (Logic circuits) Thesaurus: Integrated circuit technology; Integrated logic circuits; Logic arrays; Redundancy; VLSI Free Terms: WSI; Wafer scale integration; Regularised logic; Programmable gate arrays; Memories; Column repair; Logic circuits; Restructurable logic component; PGA; Logic Component Array; LCA Item Availability: CD-ROM. INSPEC 3690082 B90054656 C90051457 Doc Type: Journal Paper Title: FRISC-E: a 250-MIPS hybrid microprocessor Authors: Grueb, H.J.; McDonald, J.F.; Creedon, T.G. Affiliation: Rensselaer Polytech. Inst., Troy, NY, USA Journal: IEEE Circuits and Devices Magazine Vol: 6 Iss: 3 p. 16-25 Date: May 1990 Country of Publication: USA ISSN: 8755-3996 CODEN: ICDMEN CCC: 8755-3996/90/0500-0016$01.00 Language: English Treatment: Practical Abstract: A description is given of the FRISC-E, a 32-bit fast RISC (reduced instruction set computer) design using advanced differential bipolar logic. FRISC-E was designed to solve the problems caused by partitioning high-speed microprocessors, which is necessary to increase yield and reduce heat flux but requires die-to-die interconnections that cause signal propagation delays. The design and packaging of FRISC-E is described, and its use of pipelining is discussed. System architecture and performance are examined. (17 Refs.) Classification: B1265F (Microprocessors and microcomputers); B2220J (Hybrid integrated circuits); B2570B (Bipolar integrated circuits); C5130 (Microprocessor chips) Thesaurus: Bipolar integrated circuits; Hybrid integrated circuits; Microprocessor chips; Packaging; Pipeline processing; Reduced instruction set computing Free Terms: FRISC-E; RISC; Reduced instruction set computer; Advanced differential bipolar logic; High-speed microprocessors; Packaging; Pipelining; Architecture; 32 Bit; 250 MIPS Numerical Index: Word length 3.2E+01 bit; Computer execution rate 2.5E+08 IPS Item Availability: CD-ROM. INSPEC 3659903 B90044758 Doc Type: Conference Paper Title: LED array modules by new method micron bump bonding method Authors: Hatada, K.; Fujimoto, K.; Ochi, T.; Ishida, Y. Affiliation: Matsushita Electr. Ind. Co. Ltd., Osaka, Japan Conf. Title: Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium. Proceedings 1989 (Cat. No.89CH2720-1) p. 230-3 Publisher: IEEE New York, NY, USA Date: 1989 xviii+366 pp. Country of Publication: USA CCC: CH2720-1/89/0000-0230$1.00 Language: English Conf. Date: 25-27 Sept. 1989 Conf. Loc: San Francisco, CA, USA Conf. Sponsor: IEEE Treatment: Practical; Experimental Abstract: An LED (light-emitting diode) array module was developed by employing the micron bump bonding technique, in which electrodes of LSI chips and circuit substrate are press-bonded by utilizing the shrinkage stress produced in a light-setting insulating resin. The developed LED array module has a resolution of 400 DPI, and is constructed by face-down mounting of 54 LED chips and 54 driver LSIs on a glass substrate. These LED chips, which have an electrode pitch of 63.5 mu m, are disposed on the glass substrate at a pitch of 10 mu m. A dedicated bonder was developed for this assembling work. (4 Refs.) Classification: B4260D (Light emitting diodes); B2240 (Microassembly techniques) Thesaurus: Large scale integration; Lead bonding; Light emitting diodes Free Terms: LED array modules; Micron bump bonding method; LSI chips; Circuit substrate; Press-bonded; Shrinkage stress; Light-setting insulating resin; Face-down mounting; Driver LSIs; Electrode pitch; Dedicated bonder; 10 Micron Numerical Index: Size 1.0E-05 m Item Availability: CD-ROM. INSPEC 3636651 B90036091 Doc Type: Conference Paper Title: A new LSI bonding technology 'micron bump bonding technology' Authors: Hatada, K.; Fujimoto, H. Affiliation: Matsushita Electr. Ind. Co. Ltd., Osaka, Japan Conf. Title: 1989 Proceedings. 39th Electronic Components Conference (Cat. No.89CH2775-5) p. 45-9 Publisher: IEEE New York, NY, USA Date: 1989 xii+929 pp. Country of Publication: USA CCC: 0569-5503/89/0045$01.00 Language: English Conf. Date: 22-24 May 1989 Conf. Loc: Houston, TX, USA Conf. Sponsor: IEEE; Electron. Ind. Assoc Treatment: New development; Practical Abstract: The micron-bump bonding method for LSI chip bonding, which allows micron-order direct bonding between the LSI electrode and an electrode on the circuit substrate, is discussed. The shrinkage stress generated in light-setting insulation resin is utilized to apply a compressive force to the LSI chip, pressing it against the electrodes provided on a substrate. LSI chips having an interelectrode spacing of 10 mu m and 2320 electrodes was successfully gang bonded face down with high reliability. (2 Refs.) Classification: B2240 (Microassembly techniques); B2220J (Hybrid integrated circuits); B2570 (Semiconductor integrated circuits); B0170J (Product packaging) Thesaurus: Encapsulation; Flip-chip devices; Lead bonding; Packaging; VLSI Free Terms: Circuit substrate electrode; VLSI; Face down gang bonding; UV curing resin; LSI bonding technology; Micron bump bonding technology; LSI chip bonding; Micron-order direct bonding; LSI electrode; Shrinkage stress; Light-setting insulation resin; Compressive force; Interelectrode spacing; Gang bonded face down; High reliability; 10 Micron Numerical Index: Size 1.0E-05 m Item Availability: CD-ROM. INSPEC 3614302 B90027952 Doc Type: Conference Paper Title: Applications of new assembly method 'micron bump bonding method' Authors: Hatada, K.; Fujimoto, H.; Ochi, T.; Ishida, Y. Affiliation: Matsushita Electr. Ind. Co. Ltd., Osaka, Japan Conf. Title: Sixth IEEE/CHMT International Electronic Manufacturing Technology Symposium. Proceedings 1989 Japan IEMT Symposium (Cat. No.89CH2741-7) p. 45-8 Publisher: IEEE New York, NY, USA Date: 1989 xvi+366 pp. Country of Publication: USA CCC: CH2741-7/89/0000-0045$1.00 Language: English Conf. Date: 26-28 April 1989 Conf. Loc: Nara, Japan Conf. Sponsor: IEEE Treatment: Application; New development; Practical Abstract: A novel LSI chip bonding method called the micron-bump bonding method was developed, making feasible micron-order direct bonding between the LSI electrode and the electrode provided on the circuit substrate. The shrinkage stress generated in light-setting insulating resin is utilized to apply a compressive force to an LSI chip, pressing it against the electrodes on the substrate. LSI chips having an interelectrode spacing of 10 mu m and a total of 2320 electrodes were successfully gang-bonded with high reliability. This technology was also successfully applied to an LED array printer head. (2 Refs.) Classification: B2240 (Microassembly techniques) Thesaurus: Integrated circuit manufacture; Integrated circuit technology; Large scale integration; Lead bonding; Surface mount technology Free Terms: Gang bonding; Microassembly; SMT; Surface mounting; Micron bump bonding method; LSI chip bonding; Light-setting insulating resin; High reliability; LED array printer head; 10 Micron Numerical Index: Size 1.0E-05 m Item Availability: CD-ROM. INSPEC 3339605 B89023755 Doc Type: Conference Paper Title: A new LSI bonding technology 'Micron bump bonding assembly technology' Authors: Hatada, K.; Fujimoto, H.; Kawakita, T.; Ochi, T. Affiliation: Matsushita Electr. Ind. Co. Ltd., Osaka, Japan Conf. Title: Fifth IEEE/CHMT International Electronic Manufacturing Technology Symposium - Design-to-Manufacturing Transfer Cycle. Proceedings 1988 (IEEE Cat. No.88CH2648-4) p. 23-7 Publisher: IEEE New York, NY, USA Date: 1988 235 pp. Country of Publication: USA CCC: CH26484/88/0000-0023$01.00 Language: English Conf. Date: 10-12 Oct. 1988 Conf. Loc: Lake Buena Vista, FL, USA Conf. Sponsor: IEEE Treatment: Practical Abstract: A novel LSI chip bonding method called the micro-bump bonding method was developed for direct bonding between the large-scale integrated (LSI) electrode and the electrode provided on the circuit substrate. In this method, the shrinkage stress generated in light-setting insulating resin results in a compressive force on the LSI chip against the electrodes on the substrate. LSI chips having an interelectrode spacing of 10 mu m and 2320 electrodes in total were successfully gang bonded in a face-down form with high reliabilities. (1 Refs.) Classification: B2570 (Semiconductor integrated circuits); B2240 (Microassembly techniques) Thesaurus: Integrated circuit technology; Large scale integration; Lead bonding Free Terms: LSI bonding technology; Chip bonding method; Micro-bump bonding method; Direct bonding; Shrinkage stress; Insulating resin; Gang bonded; Face-down form; Reliabilities; 10 Micron Numerical Index: Size 1.0E-05 m Item Availability: CD-ROM.