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Mixed
analog-digital design and application to RFID and Biomedical systems
The
research investigates new design techniques for low power and low
voltage mixed mode analogue-digital circuits using CMOS VLSI technology
for a commercial radio frequency object identification system. The
integration of all circuitry on a single substrate has a lot of benefits
such as improving the system reliability, reducing the system size,
increasing inter-system communication speed and making system implementation
more cost effective. On the other hand, some difficulties arise as
most CMOS technologies are tuned towards digital circuit design and
have a wide spread in transistor parameters. The research is concentrating
on techniques for designing low power, low voltage analogue and digital
circuits for implementation in standard CMOS technologies.
Support:
The University of Adelaide
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Ultra
high speed analog to digital converters using SEED technology
(with Dr. Corbett and Tony Sarros)
This
project involves novel designs for very high-speed data converters
using Self Electro-optic Effect Device
(SEED). The project has two main streams, the first is the design
of novel architectures for Nyquist rate analog-to-digital converters
that operate at 10-50 GSample per second with four to five bits of
resolution, while the second stream is concerned with novel data converters
that operate at a similar number of samples per second with much higher
resolution in the order of 16-20 bits. The latter is achieved by trading
the resolution in time for the required bit resolution, hence over
sampling data converter principles are utilised. The project involves
designs at a number of system design levels that include architectural,
circuits and device level. The application of the over sampling converters
are in wideband communications surveillance systems and digital radio
receivers, which require high speed, high resolution and high linearity
data converters. The high speed Nyquist rate data converter are used
in generic wideband electronic systems that require very high speed
converters but with less demanding specifications for resolution and
linearity.
Support:
The University of Adelaide
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Very
high speed analog to digital converters using CMOS technology
(with Mr. Mike Liebelt and Yingbo Zhu)
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Digital
circuit design using neuron-MOS technology (with Associate Prof.
Abbott)
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High
speed digital arithmetic (with Peter Celinski)
In
recent years, there has been renewed interest in threshold logic,
mainly as a result of the development of a number of successful implementations
of CMOS threshold logic gates. Threshold logic enables the design
of digital integrated circuits with a significant reduction in transistor
count, area and power dissipation, and improved speed performance.
In this project, we investigate the design of arithmetic circuits
including parallel counters, adders and multipliers based in two high
performance threshold logic gate implementations which we have developed.
Support:
The University of Adelaide
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Low-power,
low-phase noise voltage-controlled oscillator using silicon on insulators
(with Associate Prof. Lim and Wan-Chul Kong)
This
research aims to develop a monolithic voltage controlled oscillator
characterised by low phase noise in silicon-on-sapphire CMOS process.
Preceding the research are structured studies that endeavour to analyse
device physics of silicon-on-sapphire CMOS, investigate phase noise
characteristic of the voltage controlled oscillator and devise a filtering
technique for lower phase noise.
Support:
The University of Adelaide, St.
Jude Medical (USA)
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High
efficiency power amplifier (with Associate Prof. Coleman and
Nazif Farid)
The
field of wireless communications has been experiencing tremendous
growth recently as the numerous advantages have made many applications
wireless. Due to the limited power available, wireless products have
to consume very little power. This requirement presents designers
with a very challenging task considering the gigahertz frequencies
at which those products are meant to function. This research looks
into the feasibility of designing a very low power transmitter in
CMOS and SOI technologies for remote monitoring applications such
as temperature sensing. The transmitter will operate in the 2.4 GHz
ISM band. Furthermore, to improve the system immunity to noise and
interference a spread spectrum transmission is used. The output power
level of interest ranges between 10 mW to 100 mW rms for reliable
transmission. Consequently, very efficient power amplifiers and back-end
circuitry such as ADCs are needed due to the power constraints.
Support:
The University of Adelaide
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Artificial
insect vision (with Associate Prof. Abbott and Leo Lee)
The
objective is to map insect vision algorithms onto VLSI to make smart
collision avoidance chips. Our goal is to apply the latest neurophysiological
models using contrast adaptation.
Support:
Australian Research Council, Sir Ross & Sir Keith Smith Foundation,
AFSOR
(USA)
- Highly programmable digital receiver design (with Dr. Marwood)