Discussion

 

A number of applications such as image processing and parallel computing require high pin counts in the 1,000-2,000 range, low power, small area, and high performance interconnections. Such requirements can not be achieved using conventional packaging technologies because of the following limitations:

Low pin count:

Due to limitations imposed by large pitch spacing.

Power requirements:

The pads and wires needed to convey signals to and from the chip are large compared to the actual bare chip and introduce parasitics proportional to the pad size and the interconnect length.

Size:

The size of a bare chip is in the order of a few millimetres square, while the size of a packaged chip is roughly in the order of 100 millimetres square, which limits the extent of miniaturisation.

Weight:

May be crucial to some applications, and a packaged chip is at least 50 to 100 times heavier than a bare die.

Limited interconnection density:

Due to limitations imposed by minimum connection widths.

Long Delay:

Interconnections both inside and outside packages are long and hence communications between electronic circuits will suffer from long time delays, which may have an adverse effect on system performance.

The main issue is to connect the inside of a chip to that of another chip. The main problem lies in the fact that, using conventional technologies, interconnection lengths vary from a few microns inside a chip to centimetres outside, while interconnect widths vary accordingly. Therefore, there is a need to search for advanced packaging technologies which would allow the requirements of high performance systems to be fulfilled. Such technologies are multichip modules and 3D packaging technology, which will be discussed in Chapters 2 and 3, respectively.