In a digital system, whenever a signal transition from **0** to **1** then to **0** occurs on an interconnect, the amount of energy consumed in charging and discharging an interconnection capacitance, *C*, is given by Energy, , where *V* is the voltage swing across the capacitor. The power consumed is the energy per transition, times the number of transitions per second, *f*, so Power, . As the capacitance is proportional to the interconnection length, the total power consumption is reduced because of the reduced parasitics [19]. For example, let us say that 10% of the system power consumption is dissipated in the interconnects when mounted on a PWB. If the product was implemented using MCM technology, the power consumption will be reduced by a factor of 5. Hence, the product would consume 8% less power than the PWB-based product. Furthermore, when such a product is implemented using 3D technology the saving will be much more because of the reduced interconnect length and the associated parasitics.

Centre for High Performance Integrated Technologies and Systems (CHIPTEC),

Adelaide, SA 5005,

March 1997