The use of a 3D packaging configuration provides access to 116 neighbors within an equal interconnect length to a centre element in the stack, in contrast to 8 neighbors to the centre element in the case of 2D packaging technology, while assuming a typical die thickness of 0.6 mm [13, 14] as illustrated in Figure 
. Hence, reduction of the interconnect length in the stack results in reduction of propagation delay between chips. Furthermore, the available vertical interconnection results in maximum utilization of the available interconnects in contrast to traditional packaging technologies where such utilization is limited by physical structures such as vias or holes or by previously routed interconnects. The accessibility in case of 3D packaging technology depends on the type of vertical interconnection employed as it is proportional to the available vertical interconnect density - which is defined as the number of signal layers per average wire pitch [15, 16]. So, area interconnection provides the most accessibility and usability in contrast to peripheral interconnections, where the usability and accessibility are limited by the periphery length of the stacked element.
Figure: A comparison between 2D and 3D packaging interms of the accessability and useablity of interconnection.