Jet Propulsion Laboratory - Advanced Flight Computing

 

The Jet Propulsion Laboratory, TRW, and nCHIP are developing an Advanced Flight Computer (AFC) [42, 43, 44], shown in Figure , using a 3D MCM technology. The duration of the project is three years, and started in 10/93. Their eventual goal is to be able to construct a complete set of spacecraft avionics as a stack of MCMs, including the AFC and other physically similar modules. The system addresses ``(i) the key microelectronics technologies that will enable the design and development of small, light weight, low power consuming, and lower cost spacecraft, (ii) the architecture of an integrated microelectronics system that includes multiple subsystems, and (iii) the implementation of such solutions by leveraging the force of the private sector as well as acting as a stimulus to the commercial industry.''

  
Figure: JPL advanced flight computing using 3D MCM technology (Adapted from JPL WEB page).

The specifications of the AFC are [44]:

• Central processing unit: TRW RH-32
• Local memory: 2.0 Mbytes + 0.5 Mbytes EDAC
• Non-volatile storage: 0.5 Mbyte EEPROM
• Programmable logic: 4 3090 Xilinx FPGA
• Operating system: VxWorks
• Programming languages: C, Ada
• Bus compatibility: VME interface available
• System integration: JPL Flight system testbed
• Advanced packaging technologies: 3D chip stacking and MCM stacking
• Multichip modules: 3 MCMs with Processor, input/output and solid state recorder
• Mass: 125 gm per MCM; 0.5 kg total
• Volume: 5 10 3 cm
• Power: 10.7 watts at 25 MHz, 2.9 watts at 5 MHz
• Performance: 15-20 MIPS at 25 MHz, 5-15 MFLOPS at 25 MHz, code dependent, scaleable
• Flight demonstration opportunities: Shuttle/MIR, Mars Pathfinder