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Raytheon - Floating Point Parallel Processor

  Raytheon has designed and is fabricating a next generation signal processor in a fully 3D stackable configuration [45]. This processor, shown in Figure gif is a two dimensional nearest neighbour toroidal mesh of Parallel Floating Point Processor (PFPP) elements based on TI's TMS320C40 DSP chip, and the system is expandable up to 64 elements. Performance parameters and the vertical interconnection technique used for stacking are not available, but the following specifications were found:

   figure1068
Figure: Raytheon Floating Point Parallel Processor.


next up previous contents
Next: Technology Issues Up: Examples of 3D Packaging Previous: Jet Propulsion Laboratory -

Said F. Al-Sarawi,
Centre for High Performance Integrated Technologies and Systems (CHIPTEC),
Adelaide, SA 5005,
March 1997