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Raytheon has designed and is fabricating a next generation signal processor in a fully 3D stackable configuration [45]. This processor, shown in Figure is a two dimensional nearest neighbour toroidal mesh of Parallel Floating Point Processor (PFPP) elements based on TI's TMS320C40 DSP chip, and the system is expandable up to 64 elements. Performance parameters and the vertical interconnection technique used for stacking are not available, but the following specifications were found:
Figure: Raytheon Floating Point Parallel Processor.
- Single precision floating point processor
- 16 node processor
- 1.5 GOPS peak, 500-800 MOPS sustained
- Scalable from 4 to 64 nodes
- Contains 51 ICs, 65 Resistors/Capacitors, 28 Resistor Networks
- Operating Frequency at 40 MHz
- 3300 Wirebonds
- Dissipates 21 Watts
- 17 in total size, 10 in under seal
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Said F.
Al-Sarawi,
Centre for High Performance Integrated Technologies and Systems (CHIPTEC),
Adelaide, SA 5005,
March 1997