Three dimensional packaging technology enhances most aspects of electronic systems such as size, weight, speed, yield and reduces power consumption. Moreover, due to the systematic elimination of faulty ICs during the assembly process of a 3D device, the yield, reliability and robustness of the end device will be high compared to a discrete implementation of such a device. Currently, 3D packaging is limited by a number of factors. Some of these limitations, such as thermal management, are a result of densification, others are due to technological limitations, such as via diameter, line width, via pitch, and line spacing. It is expected that the effect of such limitations will decrease with advances in packaging technology.
The main issues in 3D packaging are the quality, the length and the number of vertical interconnections between the stacked chips or MCMs. As seen from the above discussion, these issues have been investigated by a lot of companies and manufacturers who have developed different techniques. From our research point of view, the technology which provides the largest number and the highest quality vertical interconnections should be favoured, such as the ones described in sections 
and . Another important issue that has risen as part of this study is the accessibility to manufacturers who provide 3D technology. Even though many companies are active in 3D research and technology, few offer standard 3D products and even fewer provide access to their packaging technology. As part of this study, the issue of accessibility has been addressed by establishing links with manufacturers who provide 3D packaging technologies.
As seen from the above discussion, there are four distinct methods of stacking electronic circuits. Tables and provide a summary of most of the companies working in the area of 3D packaging, classified according to the type of elements to be stacked. Some of these companies are not mentioned in the report, however, they are listed for completeness. Moreover, Tables to summarise the companies working in the area of 3D packaging with their technology applications, accessibility to us, countries, and the vertical interconnection methods used in their packaging techniques.
| Bare Die stacking | Packaged Die stacking | ||
| Standard ICs | Custom ICs | Standard Package | Custom Package |
| Actel | IBM | Mitsubishi | CTS |
| Implex | Irvine Sensors | Thomson-CFS | Dense-Pac |
| Matsushita (MEI) | Fujitsu | Samsung Electronics | Grumman |
| Thomson-CFS | Hughes | Texas Instruments | Harris |
| Hitachi & Intel | Texas Instruments | nChip, Inc. | Hitachi |
| Valtronic, Inc. | Matsushita | NEC Corp. | Motorola |
| AT&T | Irvine Sensors | RTB Technology | |
| Cray Research, Inc. | Staktek | ||
| Harris | Trymer | ||
| MCM stacking | Wafer stacking |
| Custom Modules | Custom Wafers |
| AT&T | Mass Memory Technology |
| E-Systems | Hughes |
| Raytheon (E-Systems) | ATT |
| General Electric | NTT and Thomson-CSF |
| Hughes | General Electric & |
| Matra Marconi Space | USAF Philips Lab. |
| Matsushita (MACO) | |
| Motorola | |
| Honeywell and Coors | |
| RCMT@Berlin Uni | |
| Lockheed | |
| Company | Application | Accessibility | Country | Interconnection Technique | Ref. Page |
| Matsushita | Memories | Japan | Stacked TAB carrier (PCB) | | |
| Fujitus | Memories | Japan | Stacked TAB carrier (leadframe) | | |
| Dense-Pac | Memories | USA | Solder dipped stacks to create vertical conductors on edge | | |
| Micron Technology | Memories | USA | Solder filled holes in chip carriers and spacers | | |
| Hitachi | Memories | Japan | Solder connections between plated through hole | | |
| Irvine Sensors | Memories/ASICs | USA | Thin film `T-connects' and sputtered metal conductors | | |
| Thomson-CFS | Memories/ASICs | France | Direct laser write traces on epoxy cube face | | |
| Mitsubishi | Memories | Japan | PC boards soldered on two sides of TSOP packages | | |
| Texas Instruments | Memories/ASICs | USA | Array of TAB leads soldered to bumps on silicon substrate | | |
| Grumman Aerospace | ASICs | USA | A flip-chip bonded to faces of the stack | ||
| General Electric | ASICs | USA | Folded flex circuits | | |
| Harris | ASICs | USA | Folded flex circuits | | |
| MCC | ASICs | USA | Folded flex circuits | | |
| Matra Marconi | Memories | France | Wire bonded to an MCM substrate directly | | |
| Voltonic | ASICs | USA | Wire bonded to a substrate through an IC | | |
| Company | Application | Accessibility | Country | Interconnection Technique | Ref. Page |
| Fujitsu | ASIC | Japan | Flip-chip bonded Stacked Chips without spacers | | |
| University of Colorado & UCSD | Optoelectronic | USA | Flip-chip bonded Stacked Chips with spacers |
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| Hughes | ASIC | USA | Microbridge springs and thermomigration vias | | |
| Company | Application | Accessibility | Country | Interconnection Technique | Ref. Page |
| Matsushita | Memories | USA | Solder leads on stacked MCMs | | |
| General Electric | ASIC | USA | HDI-thin film interconnect laminated to side of stack | | |
| Harris | Memories | USA | Blind castellation interconnection | | |
| CTS Microelectronics | Memories | USA | Blind castellation interconnection | | |
| Trymer | Guidance Systems | USA | Solder dipped stacks to create vertical conductors on edge | | |
| Company | Application | Accessibility | Country | Interconnection Technique | Ref. Page |
| Raytheon - E-systems | ASIC | USA | Fuzz buttons in plastic spacer and filled vias in substrate | | |
| Technical University of Berlin | ASIC | Germany | Elastomeric connectors with electrical feedthroughs | | |
| AT&T | ASIC/ multiprocessor array | USA | Compliant anisotropic conductive material | | |
| Hughes | ASIC/avionics | USA | Microbridge springs and thermomigration vias |
& | |
| Motorola | Not in Use | USA | Solder balls on top and bottom of substrate layers | | |
| Micron Technology | Memories | USA | Stacked silicon wafers with filled vias | | |
| Lockheed | ASIC/ IR processors | USA | Stacked silicon wafers with filled vias | | |