3D VLSI packaging Technology

 

The driving forces behind the development of three-dimensional packaging technology are similar to the MCM technology, although the requirements for the 3D technology are more aggressive. These requirements include the need for significant size and weight reductions, higher performance, small delay, higher reliability and, potentially, reduced power consumption.

Section  will discuss the advantages of 3D packaging technology and its effect on system performance. Section  will provide a brief discussion of the different vertical interconnection methods used in 3D packaging, while section  will address the limitations of the 3D technology. Section  will provide a discussion.

• Advantages of 3D Packaging Technology Over Conventional Technologies
  • Size and Weight
  • Silicon Efficiency
  • Interconnect Usability and Accessibility
  • Delay
  • Noise
  • Power Consumption
  • Speed
  • Interconnect Capacity
  • Interconnection Capacity Between Packaging Levels
• Vertical Interconnections in 3D Electronics
  • Periphery Interconnection between Stacked ICs
    • Stacked Tape Carrier
    • Solder Edge Conductors
    • Thin Film Conductors on Face-of-a-Cube
    • An Interconnection Substrate Soldered to the Cube Face
    • Folded Flex Circuits
    • Wire Bonded Stacked Chips
  • Area Interconnection between Stacked ICs
    • Flip-chip Bonded Stacked Chips without Spacers
    • Flip-chip Bonded Stacked Chips with Spacers
    • Microbridge Springs and Thermomigration Vias
  • Periphery Interconnection between Stacked MCMs
    • Solder Edge Conductors
    • Thin Film Conductors on Face-of-a-Cube
    • A flip-chip bonded to faces of the stack
    • Blind Castellation Interconnection
  • Area Interconnection between Stacked MCMs
    • Arrays of Contacts between MCMs with through hole vias
• Limitations of 3D Packaging Technology
  • Thermal Management
  • Design complexity
  • Cost
  • Time to Delivery
  • Design Software
• Discussion